An IC structure includes a first transistor, an interconnect structure, a dielectric layer, a polysilicon fin, and a second transistor. The first transistor is over a substrate. The interconnect structure is over the first transistor. The dielectric layer is over the interconnect structure. The polysilicon fin includes a first portion laterally extending over the dielectric layer, and a second portion extending through the dielectric layer to a metal material within the interconnect structure. The second transistor is formed on the first portion of the polysilicon fin.

Methods of forming a self-aligned CT pillar with the same CD width as the device fins to enable PC isolation and the resulting devices are provided. Embodiments include forming a plurality of fins over a substrate; forming an oxide layer over the substrate and between each fin; removing a portion of a central fin among the plurality, a trench formed in the oxide layer; forming a CT pillar in the trench; recessing the oxide layer below an upper surface of the plurality of fins; forming a gate over the plurality of fins and CT pillar; planarizing the gate down to the CT pillar; and forming a cap layer over the gate and CT pillar.

The present invention is a laminate including: a crystal substrate; a middle layer formed on a main surface of the crystal substrate, the middle layer containing a mixture of an amorphous region in an amorphous phase and a crystal region in a crystal phase having a corundum structure mainly made of a first metal oxide; and a crystal layer formed on the middle layer and having a corundum structure mainly made of a second metal oxide. Thus, provided is a laminate having high-quality corundum-structured crystal with sufficiently suppressed crystal defects.

A vertical MOSFET includes a substrate and a first III-nitride layer of a first conductivity type and having a first dopant concentration coupled to the substrate. First trenches are within the first III-nitride layer. A second III-nitride structure of a second dopant concentration and a second conductivity type opposite to the first conductivity type are within the first trenches. A third III-nitride layer of the second conductivity type is coupled to the first III-nitride layer and the second III-nitride structure. A fourth III-nitride layer of the first conductivity type coupled to the third III-nitride layer. Second trenches are within the third and fourth III-nitride layers. A gate dielectric and a gate conductor are within the second trenches. A source conductor is coupled to an upper portion of the fourth III-nitride layer. The first III-nitride layer and the second III-nitride structure provide a charge balance structure.

A gas phase epitaxial deposition method deposits silicon, germanium, or silicon-germanium on a single-crystal semiconductor surface of a substrate. The substrate is placed in an epitaxy reactor swept by a carrier gas. The substrate temperature is controlled to increase to a first temperature value. Then, for a first time period, at least a first silicon precursor gas and/or a germanium precursor gas introduced. Then, the substrate temperature is decreased to a second temperature value. At the end of the first time period and during the temperature decrease, introduction of the first silicon precursor gas and/or the introduction of a second silicon precursor gas is maintained. The gases preferably have a partial pressure adapted to the formation of a silicon layer having a thickness smaller than 0.5 nm.

Electrotechnical thin layers which can be used as a heating resistor and/or substrate for conductive layers are produced, in established methods, at high prices and extremely slowly. This problem is solved by virtue of a redox-reactively-deposited base layer which contains graphite, is formed at room temperature and on which, in the same sense, a metal forms a micrometer-scale metal layer within minutes to a few seconds by means of a redox reaction, at room temperature and during the definitive curing process. The double layer made available in this manner is highly flexible, allows soldering on copper layers, and can be used particularly advantageously as a thin-layer heating system.

A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.

In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

A wafer includes a substrate and at least one intermediate layer formed on a surface of the substrate. The at least one intermediate layer covers the surface of the substrate at least partially. An outer surface of the at least one intermediate layer is directed away from the surface of the substrate. The wafer further includes nanostructures grown on the outer surface of the at least one intermediate layer. The at least one intermediate layer is formed in such a way that positions of growth of the nanostructures are predetermined on the outer surface of the at least one intermediate layer. At least one nanostructure material of the nanostructures is assembled at the positions of growth of the nanostructures.

A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.