A method for growing nanocrystalline diamond (NCD) on Ga.sub.2O.sub.3 to provide thermal management in Ga.sub.2O.sub.3-based devices. A protective SiN.sub.x interlayer is deposited on the Ga.sub.2O.sub.3 before growth of the NCD layer to protect the Ga.sub.2O.sub.3 from damage caused during growth of the NCD layer. The presence of the NCD provides thermal management and enables improved performance of the Ga.sub.2O.sub.3-based device.

A III-nitride tunnel junction with a modified p-n interface, wherein the modified p-n interface includes a delta-doped layer to reduce tunneling resistance. The delta-doped layer may be doped using donor atoms comprised of Oxygen (O), Germanium (Ge) or Silicon (Si); acceptor atoms comprised of Magnesium (Mg) or Zinc (Zn); or impurities comprised of Iron (Fe) or Carbon (C).

A SiC epitaxial wafer of the present invention includes a SiC single crystal substrate, and a high concentration layer that is provided on the SiC single crystal substrate and has an average value of an n-type doping concentration of 1?10.sup.18/cm.sup.3 or more and 1?10.sup.19/cm.sup.3 or less, and in-plane uniformity of the doping concentration of 30% or less.

Example embodiments relate to a hardmask composition and/or a method of forming a fine pattern by using the hardmask composition, wherein the hardmask composition includes at least one of a two-dimensional layered nanostructure and a precursor thereof, and a solvent, and an amount of the at least one of a two-dimensional layered nanostructure and the precursor is about 0.01 part to about 40 parts by weight based on 100 parts by weight of the hardmask composition.

A semiconductor structure includes a substrate, a transition body over the substrate, a group III-V intermediate body having a bottom surface over the transition body and a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a first impurity concentration at the bottom surface, a second impurity concentration at the top surface, and a variable impurity concentration that rises and falls between the bottom surface and the top surface. The first impurity concentration is greater than the second impurity concentration.

An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

A method of preparing a diamond crystal substrate for epitaxial deposition thereupon of a delta doping layer includes preparing an atomically smooth, undamaged diamond crystal substrate surface, which can be in the (100) plane, by polishing the surface and then etching the surface to remove subsurface damage caused by the polishing. The polishing can include a rough polish, for example in the (010) direction, followed by a fine polish, for example in the (011) direction, that removes the polishing tracks from the rough polishing. After etching the polished face can have a roughness Sa of less than 0.3 nm. An inductively coupled reactive ion etcher can apply the etching at a homogeneous etch rate using an appropriate gas mixture such as using argon and chlorine to remove between 0.1 and 10 microns of material from the polished surface.

A novel doping technology for semiconductor wafers has been developed, referred to as a quantum doping process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a quantized set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.