In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Implementations of the present disclosure generally relates to a transfer chamber coupled to at least one vapor phase epitaxy chamber a plasma oxide removal chamber coupled to the transfer chamber, the plasma oxide removal chamber comprising a lid assembly with a mixing chamber and a gas distributor; a first gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a second gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a third gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; and a substrate support with a substrate supporting surface; a lift member disposed in a recess of the substrate supporting surface and coupled through the substrate support to a lift actuator; and a load lock chamber coupled to the transfer chamber.

Methods for removing contamination from a surface disposed in a substrate processing system are provided herein. In some embodiments, a method for removing contaminants from a surface includes: providing a first process gas comprising a chlorine containing gas, a hydrogen containing gas, and an inert gas to a process chamber having the surface disposed within the process chamber; igniting the first process gas to form a plasma from the first process gas; and exposing the surface to the plasma to remove contaminants from the surface. In some embodiments, the surface is an exposed surface of a process chamber component. In some embodiments, the surface is a surface of a first layer disposed atop a substrate, such as a semiconductor wafer.

A semiconductor device comprising a silicon substrate on which is grown a <100 nm thick epilayer of AlAs or related compound, followed by a compound semiconductor other than GaN buffer layer. Further III-V compound semiconductor structures can be epitaxially grown on top. The AlAs epilayer reduces the formation and propagation of defects from the interface with the silicon, and so can improve the performance of an active structure grown on top.

Described herein are techniques for forming an epitaxial III-V layer on a substrate. In a pre-clean chamber, a native oxygen layer may be replaced with a passivation layer by treating the substrate with a hydrogen plasma (or products of a plasma decomposition). In a deposition chamber, the temperature of the substrate may be elevated to a temperature less than 700° C. While the substrate temperature is elevated, a group V precursor may be flowed into the deposition chamber in order to transform the hydrogen terminated (Si—H) surface of the passivation layer into an Arsenic terminated (Si—As) surface. After the substrate has been cooled, a group III precursor and the group V precursor may be flowed in order to form a nucleation layer. Finally, at an elevated temperature, the group III precursor and group V precursor may be flowed in order to form a bulk III-V layer.

A nucleation layer comprised of group III and V elements is directly deposited onto the surface of a substrate made of a group IV element. Together with a first gaseous starting material containing a group III element, a second gaseous starting material containing a group V element is introduced at a process temperature of greater than 500° C. into a process chamber containing the substrate. It is essential that at least at the start of the deposition process of the nucleation layer, a third gaseous starting material containing a group IV element is fed into the process chamber, together with the first and second gaseous starting material. The third gaseous starting material develops an n-doping effect in the deposited III-V crystal, which causes a decrease in damping at a dopant concentration of less than 1×10.sup.18 cm.sup.−3.

A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm.

Method of producing one or more transition metal dichalcogenide (MX.sub.2) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX.sub.2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H.sub.2X), at a deposition temperature of about 300° C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX.sub.2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.

A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the silicon substrate and the dielectric layer. A selective epitaxial growth process and a non-selective epitaxial growth process are performed in sequence to respectively form a first epitaxial layer and a second epitaxial layer. The first epitaxial layer does not cover the top surface of the dielectric layer. The recess is filled by the first epitaxial layer and the second epitaxial layer. Finally, the first epitaxial layer and the second epitaxial layer are planarized.