The invention provides a quantum dot manufacturing method and related quantum dot semiconductor structure. The quantum dot semiconductor structure includes: a conductive ridge on a substrate; an insulative layer covering the substrate and the conductive ridge, wherein the insulative layer includes a top portion and two sidewalls over the conductive ridge; a plurality of quantum dots respectively embedded within a plurality of silicon dioxide spacer islands, which are adhered to the sidewalls of the insulative layer; and a plurality of conductive ledges adhered to the silicon dioxide spacer islands, wherein each of the conductive ledges is a portion of an electrode with alignment to the corresponding quantum dot.

Provided is a method for manufacturing a monocrystalline substrate, the method including: a process of forming a seed layer on a base charged into a monocrystalline growth apparatus; a process of taking the base, on which the seed layer is formed, out of the monocrystalline growth apparatus and irradiating laser onto the seed layer from a lower side of the base to form a separation layer having a plurality of voids; a process of charging the base, on which the separation layer is formed, into the monocrystalline growth apparatus to form a monocrystalline layer on the separation layer; and a separation process of taking the base, on which the separation layer and the monocrystalline layer are formed, out of the monocrystalline growth apparatus to separate the monocrystalline layer from the base. Therefore, the monocrystalline layer may be grown on the flat surface of the separation layer, and the monocrystalline substrate having the excellent crystallinity and suppressed in occurrence of the defects may be prepared. That is, the monocrystalline substrate having the excellent crystallinity and suppressed in occurrence of the defects while omitting the planarization process for planarizing the surface of the flat separation layer may be prepared.

In a method for manufacturing a device fabrication wafer, an SiC epitaxial wafer that is an SiC wafer 40 having a monocrystalline SiC epitaxial layer formed thereon is subjected to a basal plane dislocation density reduction step of reducing the density of basal plane dislocations existing in the epitaxial layer of the SiC epitaxial wafer, to thereby manufacture the device fabrication wafer for use to fabricate a semiconductor device. In the basal plane dislocation density reduction step, the SiC epitaxial wafer is heated under Si vapor pressure for a predetermined time necessary to reduce the density of basal plane dislocations, without formation of a cap layer on the SiC epitaxial wafer, so that the density of basal plane dislocations is reduced with suppression of surface roughening.

A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

A manufacturing method of a thin film transistor is provided, which has advantages that there are sufficient hydrogen ions in an interlayer dielectric layer. In an annealing treatment, an amount of the hydrogen ions diffused into an active layer is sufficient, and the hydrogen ions enter a channel of the thin film transistor to fill non-bonded or unsaturated bonds of polysilicon atoms, thereby filling defects in the channel, repairing the defects of the active layer, reducing the number of unsteady states, and improving mobility and threshold voltage uniformity.

A system and method for etching workpieces in a uniform manner are disclosed. The system includes a semiconductor processing system that generates a ribbon ion beam, and a workpiece holder that scans the workpiece through the ribbon ion beam. The workpiece holder includes a plurality of independently controlled thermal zones so that the temperature of different regions of the workpiece may be separately controlled. In certain embodiments, etch rate uniformity may be a function of distance from the center of the workpiece, also referred to as radial non-uniformity. Further, when the workpiece is scanned, there may also be etch rate uniformity issues in the translated direction, referred to as linear non-uniformity. The present workpiece holder comprises a plurality of independently controlled thermal zones to compensate for both radial and linear etch rate non-uniformity.

A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

A semiconductor substrate includes a first material layer made of a first material and including a plurality of protrusions, and a second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions. Each of the protrusions includes a tip and a plurality of facets converging at the tip, and adjacent facets of adjacent protrusions are in contact with each other.

A semiconductor substrate (1) disclosed herein includes: an SiC single crystal substrate (10SB); a graphene layer (11GR) disposed on an Si plane of the SiC single crystal substrate (10SB); an SiC epitaxial growth layer (12RE) disposed above the SiC single crystal substrate (10SB) via the graphene layer (11GR); and a polycrystalline Si layer (15PS) disposed on an Si plane of the SiC epitaxial growth layer (12RE). The semiconductor substrate may include a graphite substrate or an silicon substrate disposed on a polycrystalline Si layer (15PS). The semiconductor substrate may further include an SiC polycrystalline growth layer (18PC) disposed on a C plane of the SiC epitaxial growth layer (12RE). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.