An end of polishing of a wafer is determined for each of wafers at a high accuracy. A wafer processing method includes: a first process of acquiring an initial state of a processing target surface of a wafer; a second process of forming a coating film on the wafer after the first process; a third process of polishing the processing target surface of the wafer by a polishing member based on initial polishing conditions in a state where the polishing member is in contact with the processing target surface of the wafer; a fourth process of acquiring a processed state of the processing target surface of the wafer after the third process; and a fifth process of determining an end of polishing, an insufficiency in polishing, or an excess in polishing based on the initial state and the processed state.

A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.

A method includes providing a layered structure on a substrate, the layered structure including a bottom layer formed over the substrate and a photoresist layer formed over the bottom layer, exposing the photoresist layer to a radiation source, developing the photoresist layer, patterning the bottom layer and removing portions of the substrate through openings in the patterned bottom layer. In some embodiments, a middle layer is provided between the bottom layer and the photoresist layer. The material of the bottom layer includes at least one cross-linking agent that has been functionalized to decrease its affinity to other materials in the bottom layer.

Provided is a plasma processing method capable of improving an etching selectivity of a material to be etched with respect to a mask material and reducing a roughness of a side wall of a mask pattern. The plasma processing method of selectively depositing a deposition film on the mask material with respect to the material to be etched includes controlling an etching parameter so that an incubation time of the mask material is shorter than an incubation time of the material to be etched.

A photolithography method includes dispensing a first liquid onto a first target layer formed over a first wafer through a nozzle at a first distance from the first target layer; capturing an image of the first liquid on the first target layer; patterning the first target layer after capturing the image of the first liquid; comparing the captured image of the first liquid to a first reference image to generate a first comparison result; responsive to the first comparison result, positioning the nozzle and a second wafer such that the nozzle is at a second distance from a second target layer on the second wafer; dispensing a second liquid onto the second target layer formed over the second wafer through the nozzle at the second distance from the second target layer; and patterning the second target layer after dispensing the second liquid.

A technique for suppressing a metal component from remaining at a bottom of a mask pattern when the mask pattern is formed using a metal-containing resist film. A developable anti reflection film 103 is previously formed below a resist film 104. Further, after exposing and developing the wafer W, TMAH is supplied to the wafer W to remove a surface of the anti-reflection film 103 facing a bottom of the recess pattern 110 of the resist film 104. Therefore, the metal component 105 can be suppressed from remaining at the bottom of the recess pattern 110. Therefore, when the SiO.sub.2 film 102 is subsequently etched using the pattern of the resist film 104, the etching is not hindered, so that defects such as bridges can be suppressed.

A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

A single layer process is utilized to reduce swing effect interference and reflection during imaging of a photoresist. An anti-reflective additive is added to a photoresist, wherein the anti-reflective additive has a dye portion and a reactive portion. Upon dispensing the reactive portion will react with underlying structures to form an anti-reflective coating between the underlying structure and a remainder of the photoresist. During imaging, the anti-reflective coating will either absorb the energy, preventing it from being reflected, or else modify the optical path of reflection, thereby helping to reduce interference caused by the reflected energy.

A patterning process that can be utilized in order to help form conductive lines within a dielectric layer of a metallization layer is provided. In an embodiment a first interfacial layer is patterned a first time, the first interfacial layer being located over a first hard mask layer over a dielectric layer, the patterning the first interfacial layer the first time forming a first opening, which is filled with a first dielectric material. The first interfacial layer is patterned a second time, the patterning the first interfacial layer the second time forming second openings in the first interfacial layer, at least one of the second openings exposing the first dielectric material. The first dielectric material is removed, and the dielectric layer is patterned a second time after the removing the first dielectric material using the first interfacial layer as a mask, the patterning the dielectric layer extending the second openings.