A reaction apparatus contacts a process gas on a semiconductor wafer during a wafering process. The semiconductor wafer defines a center region. The reaction apparatus includes an upper dome, a lower dome, a shaft, and a cap. The lower dome is attached to the upper dome, and the upper dome and the lower dome define a reaction chamber. The cap is positioned on the shaft within the reaction chamber for reducing heat absorbed by the center region of the semiconductor wafer. The cap is attached to a first end of the shaft. The cap includes a tube and a disc. The tube defines a tube diameter larger than a shaft diameter of the shaft. The tube circumscribes the first end of the shaft. The disc is attached to the tube and is positioned to block radiant heat from heating the center region of the semiconductor wafer.

Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.

A semiconductor device having favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer includes an island-shaped top surface. The first insulating layer is provided in contact with a top surface and a side surface of the semiconductor layer. The first conductive layer is positioned over the first insulating layer and includes a portion overlapping with the semiconductor layer. In addition, the semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer. The first insulating layer includes a third region overlapping with the first conductive layer and a fourth region not overlapping with the first conductive layer. Furthermore, the second region and the fourth region contain phosphorus or boron.

A process apparatus includes a heating module and a supporter disposed below the heating module. A process space is provided between the heating module and the supporter. The heating module includes a housing, at least one heating lamp disposed in the housing, at least one temperature sensor disposed in the housing, and a blocking plate disposed under the housing. The blocking plate spatially separates the at least one heating lamp from the process space, and the blocking plate includes at least one window spatially connecting the at least one temperature sensor to the process space.

A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.

Method for manufacturing an electronic device, comprising the steps of: forming, at a front side of a solid body of 4H-SiC having a first electrical conductivity, at least one implanted region having a second electrical conductivity opposite to the first electrical conductivity; forming, on the front side, a 3C-SiC layer; and forming, in the 3C-SiC layer, an ohmic contact region which extends through the entire thickness of the 3C-SiC layer, up to reaching the implanted region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

A resistive element in an artificial neural network, the resistive element includes a Silicon-on-insulator (SOI) substrate, and a Silicon layer formed on the Silicon-on-insulator substrate. The Silicon layer includes dopants derived from a thin film dopant layer, and the thin film dopant layer includes a programmed amount of dopant including at least one of Boron and Phosphorus.

Provided is a semiconductor device which includes a semiconductor substrate that has an upper surface and a lower surface. A hydrogen chemical concentration distribution of the semiconductor substrate in a depth direction has a first hydrogen concentration peak and a second hydrogen concentration peak disposed closer to the lower surface side of the semiconductor substrate than the first hydrogen concentration peak. An intermediate donor concentration between the first hydrogen concentration peak and the second hydrogen concentration peak is different from any of an upper surface side donor concentration between the first hydrogen concentration peak and the upper surface of the semiconductor substrate and a lower surface side donor concentration between the second hydrogen concentration peak and the lower surface of the semiconductor substrate. The intermediate donor concentration may be higher than either the upper surface side donor concentration or the lower surface side donor concentration.

Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.

A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.