A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body; and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.

Provided are a semiconductor device in which the lifetime of holes is controlled and the switching loss is suppressed, and a method of manufacturing the same. Provided are a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface, a first buffer layer of the first conductive type provided between the drift layer and the second main surface in contact with the drift layer, having a resistivity lower than that of the drift layer, and having an impurity concentration higher than that of the drift layer, and a high resistivity layer provided between the first buffer layer and the second main surface and having a resistivity higher than that of the drift layer.

Provided are a semiconductor device in which the lifetime of holes is controlled and the switching loss is suppressed, and a method of manufacturing the same. Provided are a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface, a first buffer layer of the first conductive type provided between the drift layer and the second main surface in contact with the drift layer, having a resistivity lower than that of the drift layer, and having an impurity concentration higher than that of the drift layer, and a high resistivity layer provided between the first buffer layer and the second main surface and having a resistivity higher than that of the drift layer.

Disclosed herein are methods for backside wafer dopant activation using a high-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a high-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

A method for forming a drift region of a superjunction device includes forming a drift region section having a semiconductor layer with first regions of a first doping type and second regions of a second doping type arranged alternatingly in a first lateral direction. Forming the drift region section includes: forming an implantation mask on top of a first surface of the semiconductor layer and including first openings; in a first implantation process, implanting dopant atoms of the first doping type through the first openings into the first surface; increasing a size of the first openings to obtain second openings; in a second implantation process, implanting dopant atoms of the second doping type through the second openings into the first surface; and after removing the mask, in a third implantation process, implanting dopant atoms of the first doping type into the first surface.

The present application discloses a super junction device, which includes: an N-type redundant epitaxial layer and an N-type buffer layer sequentially formed on an N-type semiconductor substrate; a trench filled super junction structure is formed on the N-type buffer layer; a back structure includes a drain region and a patterned back P-type impurity region; the N-type semiconductor substrate is removed in a back thinning process, and the N-type redundant epitaxial layer is completely or partially removed in the back thinning process; the resistivity of the N-type semiconductor substrate is 0.1-10 times the resistivity of a top epitaxial layer, the resistivity of the N-type redundant epitaxial layer is 0.1-10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer. The present application further discloses a method for manufacturing a super junction device.

The present disclosure relates generally to ion implantation, and more particularly, to systems and processes for adjusting a ribbon beam angle of an ion implantation system. An exemplary ion implantation system includes an ion source configured to generate a ribbon beam, a wafer chuck configured to hold a wafer during implantation by the ribbon beam, a dipole magnet disposed between the ion source and the wafer chuck, and a controller. The dipole magnet includes at least two coils configured to adjust a ribbon beam angle of the ribbon beam at one or more locations along a path of the ribbon beam between the ion source and the wafer held in the wafer chuck. The controller is configured to control the ion source, the wafer chuck, and the dipole magnet.

A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

The present application discloses an OTP memory. A cell structure includes a first active region and a second active region that intersect vertically; an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region; a body portion of a channel region of the PMOS is formed a drift region of the EDNMOS, a first polysilicon gate of the EDNMOS serves as a control gate, and a second polysilicon gate of the PMOS serves as a floating gate; and the PMOS is programmed by means of hot carriers generated in the drift region of the EDNMOS. The present application further discloses a method for manufacturing an OTP memory. In the present application, high-speed writing can be implemented.