Patent classifications
H01L21/288
Plating chuck
A plating chuck for holding a substrate during plating processes, wherein the substrate has a notch area (3031) and a patterned region (3032) adjacent to the notch area (3031). The plating chuck comprises a cover plate (3033) configured to cover the notch area (3031) of the substrate to shield the electric field at the notch area (3031) when the substrate is being plated.
Plating chuck
A plating chuck for holding a substrate during plating processes, wherein the substrate has a notch area (3031) and a patterned region (3032) adjacent to the notch area (3031). The plating chuck comprises a cover plate (3033) configured to cover the notch area (3031) of the substrate to shield the electric field at the notch area (3031) when the substrate is being plated.
Fabricating an RF filter on a semiconductor package using selective seeding
A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.
Fabricating an RF filter on a semiconductor package using selective seeding
A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.
Plating device and resistor
A plating device includes: an anode; a substrate holder which holds a substrate; a substrate contact which comes into contact with a peripheral edge portion of the substrate; a resistor which is disposed in a way of facing the substrate holder between the anode and the substrate holder, and is used for adjusting ion movement; and a rotation driving mechanism which causes the resistor and the substrate holder to relatively rotate. The resistor includes: a shielding region which forms an outer frame and shields the ion movement between the anode and the substrate; and a resistance region which is formed on the radially inner side of the shielding region, and has a porous structure allowing the passage of an ion. An outer diameter of the resistance region has an amplitude centering on an imaginary reference circle, and has a wave shape which is periodic and annularly continuous.
Plating device and resistor
A plating device includes: an anode; a substrate holder which holds a substrate; a substrate contact which comes into contact with a peripheral edge portion of the substrate; a resistor which is disposed in a way of facing the substrate holder between the anode and the substrate holder, and is used for adjusting ion movement; and a rotation driving mechanism which causes the resistor and the substrate holder to relatively rotate. The resistor includes: a shielding region which forms an outer frame and shields the ion movement between the anode and the substrate; and a resistance region which is formed on the radially inner side of the shielding region, and has a porous structure allowing the passage of an ion. An outer diameter of the resistance region has an amplitude centering on an imaginary reference circle, and has a wave shape which is periodic and annularly continuous.
APPARATUS FOR ELECTRO-CHEMICAL PLATING
An electrochemical plating apparatus for performing an edge bevel removal process on a wafer includes a cell chamber. The cell chamber includes two or more nozzles located adjacent to the edge of the wafer. A flow regulator is arranged with each of the two or more nozzles, which is configured to regulate an tap width of a deposited film flowing out through the each of the two or more nozzles. The electrochemical plating apparatus further includes a controller to control the flow regulator such that tap width of the deposited film includes a pre-determined surface profile. The two or more nozzles are located in radially or angularly different dispensing positions above the wafer.
SUBSTRATE AND METHOD INCLUDING FORMING A VIA COMPRISING A CONDUCTIVE LINER LAYER AND CONDUCTIVE PLUG HAVING DIFFERENT MICROSTRUCTURES
In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.
LDMOS Transistor and Method
In an embodiment, a semiconductor device includes a semiconductor substrate, a LDMOS transistor arranged in a front surface of the semiconductor substrate and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the semiconductor substrate, a conductive plug filling a first portion of the via and a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug.
WIRING BOARD AND METHOD FOR PRODUCING WIRING BOARD
A wiring board includes a substrate having main surfaces and an electrode containing Cu or Ag as a main component on at least one main surface of the substrate, wherein the electrode protrudes from the substrate, a surface of the electrode is covered by a first Ni film containing crystalline Ni as a main component, a surface of the first Ni film is covered by a second Ni film containing amorphous Ni as a main component, and the first Ni film covers a part of a first corner where a side surface of the electrode is in contact with the substrate.