The present invention relates to a cyber-physical system for optimizing a simulation model for chemical mechanical polishing based on actual measurement data of chemical mechanical polishing. The chemical mechanical polishing system includes a polishing apparatus (1) for polishing the workpiece (W) and an arithmetic system (47). The arithmetic system (47) includes a simulation model including at least a physical model configured to output an estimated polishing physical quantity including an estimated polishing rate of the workpiece (W). The arithmetic system (47) is configured to: input polishing conditions for the workpiece (W) into the simulation model; output the estimated polishing physical quantity of the workpiece (W) from the simulation model; and determine model parameters of the simulation model that bring the estimated polishing physical quantity closer to a measured polishing physical quantity of the workpiece (W).

The present invention provides a composition which is suppressed in decrease of the etching rate over time. A composition which contains; at least one of a quaternary alkyl ammonium fluoride and a hydrate of a quaternary alkyl ammonium fluoride; (A) an N-substituted amide compound that has no active hydrogen on a nitrogen atom and (B) a dipropylene glycol dimethyl ether, which serve as aprotic solvents; and an antioxidant.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.

The invention provides a polishing pad suitable for polishing at least one of semiconductor, optical, magnetic or electromechanical substrates. It includes a polyurea polishing layer and a polyurea matrix. The polyurea has a soft segment being a copolymer of aliphatic fluorine-free polymer groups and a fluorocarbon having a length of a least six carbons. The polyurea matrix being cured with a curative agent and including gas or liquid-filled polymeric microelements. The polyurea matrix has a bulk region and a transition region adjacent the bulk region that extends to the polishing layer. The polymeric microelements in the transition region decrease in thickness as they approach the polishing layer with thickness of the compressed microelements adjacent the polishing layer being less than fifty percent of a diameter of the polymeric microelements in the bulk region. The polishing layer remains hydrophilic during polishing in shear conditions.

The invention provides a polishing pad suitable for polishing at least one of semiconductor, optical, magnetic or electromechanical substrates. It includes a polyurea polishing layer and a polyurea matrix. The polyurea has a soft segment being a copolymer of aliphatic fluorine-free polymer groups and a fluorocarbon having a length of a least six carbons. The polyurea matrix being cured with a curative agent and including gas or liquid-filled polymeric microelements. The polyurea matrix has a bulk region and a transition region adjacent the bulk region that extends to the polishing layer. The polymeric microelements in the transition region decrease in thickness as they approach the polishing layer with thickness of the compressed microelements adjacent the polishing layer being less than fifty percent of a diameter of the polymeric microelements in the bulk region. The polishing layer remains hydrophilic during polishing in shear conditions.

A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other.

A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other.

A protective sheeting for use in processing a semiconductor-sized wafer has a substantially circular base sheet and a substantially annular adhesive layer applied to a peripheral portion of a first surface of the base sheet. The inner diameter of the adhesive layer is smaller than the diameter of the wafer. Further, the outer diameter of the adhesive layer is larger than the inner diameter of an annular frame for holding the wafer. A related method includes attaching the protective sheeting to a front side or a back side of the wafer via the adhesive layer on the first surface of the base sheet so that an inner peripheral portion of the adhesive layer adheres to an outer peripheral portion of the front side or the back side of the wafer, and processing the wafer after the protective sheeting has been attached to the front side or the back side thereof.