Patent classifications
H01L21/3205
Method of gap filling using conformal deposition-annealing-etching cycle for reducing seam void and bending
A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
Device for measuring bump height, apparatus for processing substrate, method of measuring bump height, and storage medium
An object is to allow for simple measurement of a bump height. There is provided a device for measuring a bump height comprising: a light sensor provided with a light source and a light-receiving element and configured to irradiate a substrate including a seed layer, a resist layer formed on the seed layer and a bump formed in an opening of the resist layer, with light emitted from the light source and to detect reflected light that is reflected from the seed layer via the resist layer and reflected light that is reflected from the bump, by the light-receiving element; and a control device configured to calculate a height of the bump relative to the seed layer, based on the reflected light from the seed layer and the reflected light from the bump and to subtract an error caused by a refractive index of the resist layer from the height of the bump calculated based on the reflected lights, so as to correct the height of the bump.
Backside metal removal die singulation systems and related methods
Implementations of methods of singulating a plurality of die included in a substrate may include forming a groove through a backside metal layer through laser ablating a backside metal layer at a die street of a substrate and singulating a plurality of die included in the substrate through removing substrate material of the substrate in the die street.
GAS SUPPLY AMOUNT CALCULATION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Gas supply amount calculation method includes: calculating flow rate of first substance gas by subtracting flow rate of second substance gas from flow rate of mixed gas of the first and second substance gas flowing through gas supply path connected to processing container configured to perform film formation by atomic layer deposition method; calculating first integrated flow rate of the first substance gas over time in remaining plurality of cycles after elapse of a predetermined number of cycles immediately after start of the film formation over a plurality of cycles; calculating average integrated flow rate per cycle by dividing the first integrated flow rate by the number of the remaining plurality of cycles; and calculating total supply amount of the first substance gas in the plurality of cycles by adding multiplication value obtained by multiplying the average integrated flow rate by the predetermined number and the first integrated flow rate.
Solid-state imaging device with multiple substrates
A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
FILM FORMING METHOD AND FILM FORMING SYSTEM
A film forming method includes: preparing a substrate having a recess within a processing container; forming a silicon-containing film on the substrate by activating a silicon-containing gas with plasma and supplying the activated silicon-containing gas to the substrate; partially modifying the silicon-containing film after the silicon-containing film closes an opening of the recess; and selectively etching the modified silicon-containing film.
IMAGING ELEMENT AND METHOD FOR MANUFACTURING IMAGING ELEMENT
An imaging element including a plurality of semiconductor chips which are bonded together is prevented from being damaged._The imaging element includes the plurality of semiconductor chips each including a semiconductor substrate and a wiring region. One of the plurality of semiconductor chips is disposed with a photoelectric conversion unit that performs photoelectric conversion of incident light. Two of the plurality of semiconductor chips each includes a first pad, surfaces of the wiring regions of the two semiconductor chips being bonded together, the first pads being disposed on the respective surfaces of the wiring regions and being joined to each other. At least one of the two semiconductor chips further includes a second pad disposed in the wiring region and an insulating film disposed between the second pad and the surface for bonding, the second pad being formed with a protrusion toward the surface for bonding.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a semiconductor substrate and an electrode. The electrode is electrically connected to the semiconductor substrate and located on the semiconductor substrate. The electrode has a lower metal layer, an upper metal layer and an intermediate layer. The lower metal layer is located at a side closer to the semiconductor substrate. The upper metal layer is located above the lower metal layer. The intermediate layer is located between the lower metal layer and the upper metal layer. Each of the lower metal layer and the upper metal layer is made of aluminum or an aluminum alloy. In the aluminum alloy, an element is added to aluminum. The intermediate layer is made of material that is more difficult to react with a hydroxyl group than the lower metal layer and the upper metal layer.
MANUFACTURING METHOD FOR SEMICONDUCTOR SILICON WAFER
The substrate is doped with P, has a resistivity adjusted to 1.05 mΩ.Math.cm or less, and includes defects, formed in the crystal by the aggregation of P, which are Si—P crystal defects substantially. The method includes a step of forming a silicon oxide film on the backside of the substrate with a thickness of 300 nm or more and 700 nm or less, a step of mirror-polishing the substrate, and after the mirror-polishing step, a heat treatment step of the substrate mounted on a substrate holder made of Si or SiC, on the holder surface a silicon oxide film is formed with the thickness between 200 nm and 500 nm, wherein the thickness X of the silicon oxide film of the holder and the thickness Y of that on the backside of the substrate satisfy a relational expression Y=C−X, where C is a constant between 800 and 1000.
TESTING A SEMICONDUCTOR DIE USING TEMPORARY TEST PADS APPLIED TO CONDUCTIVE PADS OF THE SEMICONDUCTOR DIE
A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.