A vapor deposition apparatus includes an exhaust regulator provided in an exhaust pipe to regulate exhaust of the reaction chamber and including: a hollow frustum upstream baffle having a larger first opening near a reaction chamber than a second opening near an exhaust device; and a hollow frustum downstream baffle provided near the exhaust device with respect to the upstream baffle and having a larger third opening near the reaction chamber than a fourth opening near the exhaust device. The upstream baffle and downstream baffle are designed so that B/A and C/A are 0.33 or less, at least one of B/A and C/A is 0.26 or less, and (B+C)/A is 0.59 or less, where an inner diameter of the exhaust pipe and diameters of the first and third openings are A, a diameter of the second opening is B and a diameter of the fourth opening is C.

A gettering property evaluating method for a wafer includes: a gettering layer forming step of polishing a back surface opposite to a front surface of a semiconductor wafer by use of a polishing wheel to form polishing marks on the back surface and to form a gettering layer inside the semiconductor wafer and beneath the polishing marks; an imaging step of imaging at least a unit region of the back surface formed with the polishing marks by imaging means; a counting step of counting the number of the polishing marks having a width of 10 to 500 nm present in the unit region imaged; and a comparing step of comparing the number of the polishing marks counted by the counting step with a predetermined value to determine whether or not the counted number is not less than the predetermined value.

A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body, removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C., and forming a first load terminal structure at the first side of the semiconductor body.

Disclosed embodiments apply electron beams to substrates for microelectronic workpieces to improve plasma etch and deposition processes. The electron beams are generated and directed to substrate surfaces using DC (direct current) biasing, RF (radio frequency) plasma sources, and/or other electron beam generation and control techniques. For certain embodiments, DC-biased RF plasma sources, such as DC superposition (DCS) or hybrid DC-RF sources, are used to provide controllable electron beams on surfaces opposite a DC-biased electrode. For certain further embodiments, the DC-biased electrode is pulsed. Further, electron beams can also be generated through electron beam extraction from external and/or non-ambipolar sources. The disclosed techniques can also be used with additional electron beam sources and/or additional etch or deposition processes.

A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen concentration in a semiconductor wafer. On the basis of information about the extrinsic dopant concentration and the intrinsic oxygen concentration as well as information about a generation rate or a dissociation rate of oxygen-related thermal donors in the semiconductor wafer, a process temperature gradient is determined for generating or dissociating oxygen-related thermal donors to compensate for a difference between a target dopant concentration and the extrinsic dopant concentration.

A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.

A workpiece evaluating method evaluates the gettering property of a device wafer having a plurality of devices formed on the front side of the wafer and having a gettering layer formed inside the wafer. The method includes the steps of applying excitation light for exciting a carrier to the wafer, applying microwaves to a light applied area where the excitation light is applied and also to an area other than the light applied area, measuring the intensity of the microwaves reflected from the light applied area and from the area other than the light applied area, subtracting the intensity of the microwaves reflected from the area other than the light applied area from the intensity of the microwaves reflected from the light applied area to thereby obtain a differential signal, and determining the gettering property of the gettering layer according to the intensity of the differential signal obtained above.

A semiconductor device includes a silicon semiconductor body having a main surface and a nitrogen concentration which is lower than about 2*10.sup.14 cm.sup.−3 at least in a first portion of the silicon semiconductor body, the first portion extending from the main surface to a depth of about 50 μm. The nitrogen concentration increases with a distance from the main surface at least in the first portion. The semiconductor device further includes a field-effect structure arranged next to the main surface.

Provided is a method of producing an epitaxial silicon wafer having high gettering capability resulting in even more reduced white spot defects in a back-illuminated solid-state imaging device. The method includes: a first step of irradiating a surface of a silicon wafer with cluster ions of C.sub.nH.sub.m (n=1 or 2, m=1, 2, 3, 4, or 5) generated using a Bernas ion source or an IHC ion source, thereby forming, in the silicon wafer, a modifying layer containing, as a solid solution, carbon and hydrogen that are constituent elements of the cluster ions; and a subsequent second step of forming a silicon epitaxial layer on the surface. In the first step, peaks of concentration profiles of carbon and hydrogen in the depth direction of the modifying layer are made to lie in a range of more than 150 nm and 2000 nm or less from the surface.

The present invention is a method for manufacturing a bonded SOI wafer, including: preparing, as a base wafer, a silicon single crystal wafer whose initial interstitial oxygen concentration is 15 ppma or more ('79ASTM); forming a silicon oxide film on a surface of the base wafer by heating the base wafer in an oxidizing atmosphere such that a feeding temperature at which the base wafer is fed into a heat treatment furnace for the heat treatment is 800° C. or more, and the base wafer is heated at the feeding temperature or higher; bonding the base wafer to the bond wafer with the silicon oxide film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a method for manufacturing a bonded SOI wafer by a base oxidation method which suppresses the formation of oxide precipitates in a base wafer while suppressing slip dislocation.