There is provided a technique that includes (a) forming a film on a substrate by exposing the substrate to a film-forming agent under a first temperature; (b) heat-treating the film under a second temperature higher than the first temperature; (c) altering the heat-treated film by exposing the heat-treated film to an altering agent; and (d) removing the altered film by exposing the altered film to a removing agent.

A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a groove through a backside metal layer through laser ablating a backside metal layer at a die street of a substrate and singulating a plurality of die included in the substrate through removing substrate material of the substrate in the die street.

Techniques herein include methods for forming a direct write, tunable stress film and methods for correcting wafer bow using said stress film. The method can be executed on a coater-developer tool or track-based tool. The stress film can be based on a film that undergoes crosslinking/decrosslinking under external stimulus where direct write is achieved by, but is not limited to, 365 nm exposure and subsequent cure is used to “pattern-in” stress. No develop step may be required, which provides additional significant benefit in conserving film planarity. An amount of bow (or internal stress to create or affect a bow signature) can be tuned with exposure dose, bake temperature, bake time and number of bakes.

The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

A semiconductor structure and a method for forming the same are provided. In one form, a semiconductor structure includes: a substrate and protruding portions protruding from the substrate in sub-device regions; channel structure layers located on the protruding portions and spaced apart from the protruding portions, where each of the channel structure layers includes one or more channel layers spaced apart from each other; a dielectric wall located on the substrate between adjacent sub-device regions in a longitudinal direction, where the dielectric wall includes a main dielectric wall portion protruding from the substrate and dielectric wall protrusions protruding from the main dielectric wall portion in the longitudinal direction, where the dielectric wall protrusions are in contact with side walls of the channel layers; gate structures located on the sub-device regions, spanning tops of the channel structure layers in the sub-device regions, and surrounding the channel layers exposed from the dielectric wall; and source/drain doped layers located on the protruding portions on two sides of the gate structures and in contact with the channel structure layers. In forms of the present disclosure, an influence of the dielectric wall on a stress applied by the source/drain doped layers to the channel layers is reduced, and performance of the semiconductor structure is optimized.

A semiconductor device includes a substrate that includes an active pattern, a channel pattern disposed on the active pattern, where the channel pattern includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, and a gate electrode disposed on the semiconductor patterns. The gate electrode includes a plurality of portions that are respectively interposed between the semiconductor patterns, and the source/drain pattern includes a buffer layer in contact with the semiconductor patterns and a main layer disposed on the buffer layer. The buffer layer contains silicon germanium (SiGe) and includes a first semiconductor layer and a first reflow layer thereon. A germanium concentration of the first reflow layer is less than that of the first semiconductor layer.

A fabrication method of a semiconductor substrate includes: performing a chemical mechanical polishing process on a silicon carbide wafer; and performing a heating process on the silicon carbide wafer to remove a naturally formed oxide layer, to remove contaminants, to obtain a scratch-free surface, and to planarize, wherein the heating process includes: heating a chamber of a furnace and the silicon carbide wafer to T degrees Celsius for a time t, and introducing hydrogen, argon, nitrogen, or/and hydrogen chloride into the chamber; and then cooling down the furnace.

A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H.sub.2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.