Provided is a SiC substrate treatment method for, with respect to a SiC substrate (40) that has, on its surface, grooves (41), activating ions while preventing roughening of the surface of the substrate. In the method, an ion activation treatment in which the SiC substrate (40) is heated under Si vapor pressure is performed to the SiC substrate (40) has, on its surface, an ion implantation region (46) in which ions have been implanted, and has the grooves (41) provided in a region including at least the ion implantation region (46), thereby ions that are implanted in the SiC substrate (40) is activated while etching the surface of the substrate.

A field effect transistor according to the present invention includes a semiconductor layer including a groove, an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove and a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove and having parts being in contact with an upper surface of the insulating film on both sides of the opening, wherein the gate electrode has a T-shaped sectional shape in which a width of an upper end is larger than a width of the upper surface of the insulating film.

A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

According to one embodiment, a semiconductor device includes a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating unit, a void, a gate insulating film and a gate electrode. The second semiconductor region provides on a part of the first semiconductor region. The third semiconductor region provides on one other part of the first semiconductor region. The insulating unit provides on a part of the second semiconductor region. The void provides at a lower part of the insulating unit. The gate insulating film provides on a part of the first semiconductor region between the second semiconductor region and the third semiconductor region. The gate electrode provides on the gate insulating film. A position in a first direction of at least a part of the void is between the insulating unit and the third semiconductor region.

Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

Methods of forming a low-resistance source/drain feature for a multi-gate device are provided. A example method includes forming a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, forming a bottom dielectric layer over the substrate, depositing a first epitaxial layer over the inner spacers and the sidewalls of the plurality of the channel layers, performing a thermal treatment to reshape the first epitaxial layer, after the performing of the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer. The first epitaxial layer includes germanium and the second epitaxial layer is free of germanium.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a groove through a backside metal layer through laser ablating a backside metal layer at a die street of a substrate and singulating a plurality of die included in the substrate through removing substrate material of the substrate in the die street.

A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.

Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.