H01L21/443

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, DISPLAY DEVICE, AND ELECTRONIC DEVICE

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, DISPLAY DEVICE, AND ELECTRONIC DEVICE

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

Semiconductor device having plurality of 2T2C DRAM memory cells

An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.

Selector transistor with metal replacement gate wordline

A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

Selector transistor with metal replacement gate wordline

A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

Semiconductor device, manufacturing method thereof, display device, and electronic device

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

Semiconductor device, manufacturing method thereof, display device, and electronic device

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

PRODUCING AN OHMIC CONTACT AND ELECTRONIC COMPONENT WITH OHMIC CONTACT

A method for producing an ohmic contact for an electronic part, wherein a layer consisting of a semiconductor is applied to a substrate is disclosed. A surface to be contacted of the applied semiconductor is wet-chemically etched, which is rinsed with radicals. An electrical conductor or a semiconductor is applied to the surface rinsed with radicals. An electronic component having several semiconductor layers on a substrate is also disclosed. A top layer on the one or more semiconductor layers is applied to the substrate. The top layer consists of an electrically non-conductive dielectric having an access through the top layer to a semiconductor layer, wherein adjacent semiconductor layers consist of different II-VI semiconductors. The access is at least partially filled with a II-VI semiconductor. A metallic contact applied to the II-VI semiconductor extends to the outer side of the top layer or projects outwardly relative to the top layer.

PRODUCING AN OHMIC CONTACT AND ELECTRONIC COMPONENT WITH OHMIC CONTACT

A method for producing an ohmic contact for an electronic part, wherein a layer consisting of a semiconductor is applied to a substrate is disclosed. A surface to be contacted of the applied semiconductor is wet-chemically etched, which is rinsed with radicals. An electrical conductor or a semiconductor is applied to the surface rinsed with radicals. An electronic component having several semiconductor layers on a substrate is also disclosed. A top layer on the one or more semiconductor layers is applied to the substrate. The top layer consists of an electrically non-conductive dielectric having an access through the top layer to a semiconductor layer, wherein adjacent semiconductor layers consist of different II-VI semiconductors. The access is at least partially filled with a II-VI semiconductor. A metallic contact applied to the II-VI semiconductor extends to the outer side of the top layer or projects outwardly relative to the top layer.

TWO-DIMENSIONAL (2D) MATERIAL FOR OXIDE SEMICONDUCTOR (OS) FERROELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICE
20220246766 · 2022-08-04 ·

The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.