A field-effect transistor including: a source electrode and a drain electrode; a gate electrode; a semiconductor layer; and a gate insulating layer, wherein the gate insulating layer is an oxide insulator film including A element and B element, the A element being one or more selected from the group consisting of Zr and Hf and the B element being one or more selected from the group consisting of Be and Mg.

A field-effect transistor including: a source electrode and a drain electrode; a gate electrode; a semiconductor layer; and a gate insulating layer, wherein the gate insulating layer is an oxide insulator film including A element and B element, the A element being one or more selected from the group consisting of Zr and Hf and the B element being one or more selected from the group consisting of Be and Mg.

A coating liquid for forming an oxide, the coating liquid including: A element, which is at least one alkaline earth metal; and B element, which is at least one selected from the group consisting of gallium (Ga), scandium (Sc), yttrium (Y), and lanthanoid, wherein when a total of concentrations of the A element is denoted by C.sub.A mg/L and a total of concentrations of the B element is denoted by C.sub.B mg/L, a total of concentrations of sodium (Na) and potassium (K) in the coating liquid is (C.sub.A+C.sub.B)/10.sup.3 mg/L or less and a total of concentrations of chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), and copper (Cu) in the coating liquid is (C.sub.A+C.sub.B)/10.sup.3 mg/L or less.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A plating chuck for holding a substrate during plating processes, wherein the substrate has a notch area (3031) and a patterned region (3032) adjacent to the notch area (3031). The plating chuck comprises a cover plate (3033) configured to cover the notch area (3031) of the substrate to shield the electric field at the notch area (3031) when the substrate is being plated.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Disclosed are a thin film transistor including a substrate and a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode formed on the substrate and a method of fabricating the thin film transistor, wherein the gate insulating film is made of a high dielectric ternary material, A.sub.2-XB.sub.XO.sub.3, wherein A is any one selected from the group consisting of aluminum, silicon, gallium, germanium, neodymium, gadolinium, vanadium, lutetium, and actinium, B is any one selected from the group consisting of yttrium, lanthanum, zirconium, hafnium, tantalum, titanium, vanadium, nickel, silicon, and ytterbium, and A is an element different from B. The gate insulating film may be formed through a solution process, and a high-quality insulating film may be obtained through heat treatment at low temperature.

Disclosed are a thin film transistor including a substrate and a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode formed on the substrate and a method of fabricating the thin film transistor, wherein the gate insulating film is made of a high dielectric ternary material, A.sub.2-XB.sub.XO.sub.3, wherein A is any one selected from the group consisting of aluminum, silicon, gallium, germanium, neodymium, gadolinium, vanadium, lutetium, and actinium, B is any one selected from the group consisting of yttrium, lanthanum, zirconium, hafnium, tantalum, titanium, vanadium, nickel, silicon, and ytterbium, and A is an element different from B. The gate insulating film may be formed through a solution process, and a high-quality insulating film may be obtained through heat treatment at low temperature.