A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.

In a surface treatment method for a gallium oxide-based semiconductor substrate, a surface of the gallium oxide-based semiconductor substrate is flattened by dry etching with a self-bias of 150 V or more. After the surface of the gallium oxide-based semiconductor substrate is flattened, the surface of the gallium oxide-based semiconductor substrate is washed with a chemical solution containing H.sub.2SO.sub.4 to expose a step terrace structure on the surface of the gallium oxide-based semiconductor substrate.

In a surface treatment method for a gallium oxide-based semiconductor substrate, a surface of the gallium oxide-based semiconductor substrate is flattened by dry etching with a self-bias of 150 V or more. After the surface of the gallium oxide-based semiconductor substrate is flattened, the surface of the gallium oxide-based semiconductor substrate is washed with a chemical solution containing H.sub.2SO.sub.4 to expose a step terrace structure on the surface of the gallium oxide-based semiconductor substrate.

The present disclosure provides a gallium oxide semiconductor structure, a vertical gallium oxide-based power device, and a preparation method. An unintentionally doped gallium oxide layer (110) is transferred to a highly doped and highly thermally conductive heterogeneous substrate (200) by bonding and thinning; then a heavily doped gallium oxide layer (120) is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure including the heterogeneous substrate (200), the gallium oxide layer (110), and the heavily doped gallium oxide layer (120) stacked in sequence. In the vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure, the gallium oxide layer (110) is a thicker intermediate layer and a carrier concentration of the gallium oxide layer (110) is less than that of the heavily doped gallium oxide layer (120). Therefore, the breakdown voltage of the device is also increased through structural design. The highly thermally conductive heterogeneous substrate (200) improves the heat dissipation performance of the device. The device with multiple Fin structures provides a large amount of current.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

A metal removal method which includes: a reaction step of bringing a treatment gas containing a fluorine-containing interhalogen compound and a metal-containing material containing a metal element into contact with each other to generate metal fluoride which is a reaction product of the fluorine-containing interhalogen compound and the metal element; and a volatilization step of heating the metal fluoride under an inert gas atmosphere or in a vacuum environment for volatilization. The metal element is at least one kind selected from iron, cobalt, nickel, selenium, molybdenum, rhodium, palladium, tungsten, rhenium, iridium, and platinum. Also disclosed is a dry etching method using the metal removal method and a production method for a semiconductor element using the dry etching method.

A metal removal method which includes: a reaction step of bringing a treatment gas containing a fluorine-containing interhalogen compound and a metal-containing material containing a metal element into contact with each other to generate metal fluoride which is a reaction product of the fluorine-containing interhalogen compound and the metal element; and a volatilization step of heating the metal fluoride under an inert gas atmosphere or in a vacuum environment for volatilization. The metal element is at least one kind selected from iron, cobalt, nickel, selenium, molybdenum, rhodium, palladium, tungsten, rhenium, iridium, and platinum. Also disclosed is a dry etching method using the metal removal method and a production method for a semiconductor element using the dry etching method.

A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.

A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.