Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).

A light fixture has a translucent tubular bulb. At least one end cap is located at one end of the translucent tubular bulb. A light engine is disposed in the translucent tubular bulb. The light engine has a leadframe on which a plurality of semiconductor light elements is arranged. The fixture may include an electronic driver. The electronic driver includes a plurality of electronic components. At least one of the plurality of electronic components is arranged inside the transparent tubular bulb.

A sensor chip package assembly and an electronic device having the sensor chip package assembly are disclosed, where the sensor chip package assembly includes: a metal substrate (100) which has a bonding pad region (11) and a placement region (12), the bonding pad region having a plurality of metal bonding pads (13); a sensor chip (200) which is located on an upper surface of the metal substrate, and the sensor chip having a plurality of sensor chip bonding pads (21); an electrical connection assembly (300) which electrically connects a metal bonding pad and a sensor chip bonding pad; and a packaging material cover (400) which covers the metal substrate, the sensor chip and the electrical connection assembly, where any two adjacent metal bonding pads are spaced in an insulated manner by the packaging material cover.

A composite including a metal member and a resin mold formed jointed to a surface of the metal member is provided, wherein the metal member has a roughened portion in a joint to the resin mold in the surface, and in a specific interface region including a joint interface between the roughened portion and the resin mold, the average volume in a unit area of voids between the roughened portion and the resin mold is 0.05 μm.sup.3 or smaller per 1 μm.sup.2 of a plane generally parallel to the joint interface, and the maximum dimension of the void is 1000 nm or smaller.

A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

A leadframe wherein the outer sidewalls of the leadframe that are exposed by sawing during singulation are comprised of greater than 50% solder. A leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised of greater than 50% solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised primarily of solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised entirely of solder.

The disclosed embodiments of electronic packages include electrical contact pad features present on all sides of the package that facilitate simple and low cost electrical connections to the package made through a mechanical contacting scheme. In an embodiment, an electronic package comprises: a metal leadframe having a first leadframe portion having a first thickness and a second leadframe portion having a second thickness that is less than the first thickness, the second leadframe portion defining electrical contact pads; a silicon die attached to the second leadframe portion and overlying a space formed in the leadframe by the first and second leadframe portions; and wirebonds coupling the silicon die to the electrical contact pads. A method of fabricating the electronic package is also disclosed.

In a semiconductor device (4), a semiconductor chip (10) is mounted on a die pad (6) which has a die pad overhang portion (6a) and leads (9) are arranged around and apart from the die pad (6). The leads (9) and the semiconductor chip (10) are electrically connected and are covered with a sealing resin (8). A concave portion (7e) is formed on the outer side of each lead (9), i.e., the far side from the die pad. A lead concave surface (7d) facing the concave portion (7e) includes a forward-tapered lead slope surface (7h). Side surface of the sealing resin (8) has a step of a staircase shape formed from the first and the second resin side surfaces (8a and 8b). A tip of the lead (9) protrudes past the first resin side surface (8a).

Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.

A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.