A cold plate having a copper base plate and a plurality of fins on the copper base plate. The fins are porous and made by 3D printing a copper-silver alloy on the copper base plate. Alternatively, the fins can be 3D printed and then adhered to the copper base plate with a brazing material. The copper base plate is placed on electronics to be cooled, such as a chip package, using a thermal interface material. An optional manifold can be placed on the copper base plate for circulating a coolant across the fins.

The present disclosure relates to use of 193-nm excimer laser-based lift-off (LLO) of Al.sub.0.26Ga.sub.0.74N/GaN High-electron mobility transistors (HEMTs) with thick (t>10 μm) AlN heat spreading buffer layers grown over sapphire substrates. The use of the thick AlN heat spreading layer resulted in thermal resistance (R.sub.th) of 16 Kmm/W for as-fabricated devices on sapphire, which is lower than the value of ≈25-50 Kmm/W for standard HEMT structures on sapphire without the heat-spreaders. Soldering the LLO devices onto a copper heat sink led to a further reduction of R.sub.th to 8 Kmm/W, a value comparable to published measurements on bulk SiC substrates. The reduction in R.sub.th by LLO and bonding to copper led to significantly reduced self-heating and drain current droop. A drain current density as high as 0.9 A/mm was observed despite a marginal reduction of the carrier mobility (≈1800 to ≈1500 cm.sup.2/Vs). This is the highest drain current density and mobility reported to-date for LLO AlGaN/GaN HEMTs.

An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.

A heat sink includes: a base plate; and at least one fin secured to the base plate; wherein the base plate has at least one through hole that extends in a first direction parallel to a surface of the base plate, wherein the at least one fin has a projection inserted into the at least one through hole, and wherein, in a second direction that is parallel to the surface of the base plate and that is perpendicular to the first direction, both end surfaces of the projection are in contact with inner wall surfaces of the at least one through hole entirely in a third direction parallel to a thickness direction of the base plate.

Provided are a method of manufacturing a diamond-graphene hybrid heat spreader-thermal interface material assembled thermal management material including: (a) preparing a planar diamond base material; and (b) converting a predetermined thickness of at least a partial area of one side or both sides of the diamond base material into vertical graphene, wherein the diamond base material serves as a heat spreader, and a graphene layer formed on the diamond base material serves as a thermal interface material (TIM) or a heat sink, and a method of modulating the diamond-graphene hybrid thermal management material including modulating the thermal management material by attaching a heterogenous member to the surface of the diamond-graphene hybrid thermal management material and pressurizing the attached structure.

A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) structure, and a lid structure. The package structure is disposed on the substrate. The TIM structure is disposed on the package structure. The TIM structure includes a metallic TIM layer and a non-metallic TIM layer in contact with the metallic TIM layer, and the non-metallic TIM layer surrounds the metallic TIM layer. The lid structure is disposed on the substrate and the TIM structure.

Embedded die packaging for semiconductor devices and methods of fabrication wherein conductive vias are provided to interconnect contact areas on the die and package interconnect areas. Before embedding, a protective masking layer is provided selectively on regions of the electrical contact areas where vias are to be formed by laser drilling. The material of the protective masking layer is selected to protect against over-drilling and/or to control absorption properties of surface of the pad metal to reduce absorption of laser energy during laser drilling of micro-vias, thereby mitigating physical damage, overheating or other potential damage to the semiconductor device. The masking layer may be resistant to surface treatment of other regions of the electrical contact areas, e.g. to increase surface roughness to promote adhesion of package dielectric.

A semiconductor package is provided. The semiconductor package includes a segmented inset lid that is divided into a primary component and one or more secondary components, with each secondary component being coupled to the primary component by a compliant liquid-tight adhesive; wherein the primary component is a continuous region including i) a first surface, ii) a second surface, and iii) a boundary surface, the first surface including one or more integrated heat sink surfaces or one or more routing features to promote coolant distribution, the second surface contacting one or more semiconductor dies, and the boundary surface forming a sealing surface with a semiconductor substrate; wherein each secondary component contacts at least one other semiconductor die and forms a water-tight seal with the primary component; and a removable flow cover coupled with the segmented inset lid to form a seal along the boundary surface.