Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate has a first recess and a plurality of second recesses at the bottom of the first recess. In an embodiment a die is coupled to the substrate by a die attach film (DAF), where the die sits in the first recess. In an embodiment, a surface of the DAF seals the second recesses.

graphite composite laminated heat-dissipating structure and a manufacturing method thereof are disclosed. The structure includes a metal substrate and a graphite heat-dissipating layer. The metal substrate has a first surface having a roughness ranging between 0.01 and 10 μm. The graphite heat-dissipating layer is composed of pure graphite and is directly formed on the first surface by means of physical vapor deposition using a carbon sputtering target. The graphite heat-dissipating layer has a thickness ranging between 0.05 and 2 μm. The manufacturing method includes S1: directly forming a graphite heat-dissipating layer on a first surface of a metal substrate by means of physical vapor deposition using a carbon sputtering target after the metal substrate has received plasma treatment or infrared heating; and S2: stopping the physical vapor deposition when the graphite heat-dissipating layer has a thickness ranging between 0.05 and 2 μm.

Self-cooling semiconductor resistor and manufacturing method thereof are provided. The resistor comprises: multiple N-type and P-type wells in a semiconductor substrate, first polysilicon gates on each N-type well, second polysilicon gates on each P-type well, and metal interconnect layers. The multiple N-type and P-type wells are arranged alternately in row and column direction, respectively. N-type and P-type deep doped regions are formed on each N-type and P-type well, respectively. The first and second polysilicon gates are N-type and P-type deep doped respectively, and there is no gate oxide layer between the first and second polysilicon gates and the semiconductor substrate. The metal interconnect layers connect the multiple first and second polysilicon gates as an S-shaped structure. In the present application, the flow direction of heat is from the inside of the resistor to its surface, thereby realizing heat dissipation and cooling.

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

Disclosed herein are power electronic modules formed by directly bonding a heat sink to a dielectric substrate using transition liquid phase bonding.

A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

A cooling plate for cooling microchip having redundant cooling fluid circulation. A primary fluid cooling loop removes heat directly from the microchip. A secondary cooling loop acts as a condenser for two phase cells, thus removing heat indirectly from the microchip. The cold plate may be fabricated as two parts bottom plate and top plate, wherein the primary cooling loop is formed in the bottom plate and the secondary cooling loop is formed in the top plate. Two-phase, self-contained cells may be immersed in the primary cooling loop and act to transport heat from the microchip to the secondary cooling loop.

Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

A cost-effective process and structure is provided for a thermal dissipation element for semiconductor device packages incorporating antennas that can incorporate RF/EMI shielding from the antenna elements. Certain embodiments provide incorporated antenna element structures as part of the same process. These features are provided using a selectively-plated thermal dissipation structure that is formed to provide shielding around semiconductor device dies that are part of the package. In some embodiments, the thermal dissipation structure is molded to the semiconductor device, thereby permitting a thermally efficient close coupling between a device die requiring thermal dissipation and the dissipation structure itself.

Systems and methods for cooling integrated circuits and other chop-based electronic devices use plasmonic absorption and emission of near infrared (NIR) radiation. Nanostructure arrays tuned to appropriate infrared wavelengths emit NIR from a hot chip substrate to other nanostructure arrays at the chip outer package, which absorb the NIR and transmit it away from the package outer surface.