A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.

A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

The one end portion of the connector of the semiconductor device includes: a horizontal portion; a first inclined portion that is connected to the horizontal portion and is located closer to the tip end side of the one end than the horizontal portion, and the first inclined portion having a shape inclined downward from the horizontal portion; and a control bending portion that is connected to the first inclined portion and positioned at the tip of the one end portion, and the control bending portion bent downwardly along the bending axis direction. The lower surface of the control bending portion is in contact with an upper surface of the second terminal.

In a first step of a method of manufacturing a semiconductor device, a portion to be the first lead frame is formed by selectively punching a metal plate, furthermore, notch portions depressed in the reference direction are formed on both side surfaces of a portion, of the first lead frame where the first bent portion is formed, in line contact with the first conductive layer in the reference direction; in the second step of the method, a first bent portion is formed by bending the one end of the first lead frame so as to protrude downward along the reference direction; and in the third step of the method, the upper surface of the first conductive layer and the lower surface of the first bent portion of the first lead frame are joined at the end of the substrate, by the first conductive bonding material, furthermore, the upper surface of the first conductive layer and the notch portions of the first bent portion are joined, by embedding a part of the first conductive bonding material in the notch portions.

A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.

A method of manufacturing a component carrier includes a step of stacking and connecting a first component and a second component to one another to form a cluster and thereafter, a step of inserting the cluster into a cavity of a base structure. A component carrier has a base structure with a cavity; a cluster having a first component stacked and connected with a second component, wherein the cluster is arranged in the cavity. A height difference between opposing lateral sidewalls of the cluster is less than 15 m.

A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame.

A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.

Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.

A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.