The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.

Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.

A system for processing a substrate and a method for processing a substrate are disclosed. The system for processing a substrate includes a processing chamber configured to receive the substrate, wherein the substrate is exposed to an etchant in the processing chamber to remove a portion of the substrate and generate access to the substrate. A by-product in the etching solution; and a by-product removing section configured to convert the by-product into a precipitate and remove the precipitate, thereby removing the by-product. The Etching solution is circulated back to the processing chamber after the by-product is removed.

A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.

A protective film-forming composition including good mask (protection) function against a wet etching liquid and a high dry etching rate during processing of semiconductor substrates, including good coverage even in stepped substrates, and from which flat films can be formed due to a small difference in film thickness after embedding; a protective film produced using said composition; a substrate with a resist pattern; and a method for manufacturing a semiconductor device. A protective film-forming composition which protects against a semiconductor wet etching liquid, wherein a reaction product (P) of a diepoxy compound (B) and an bifunctional proton-generating compound (C) contains a structure represented by formula (1) (in formula (1), Ar represents a C6-40 aryl group, n represents an integer of 2-10, —Y— represents —OCO—, —O— or —S—, and * represents the bonding site with the reaction product (P) molecule terminal). The protective film-forming composition further includes an organic solvent (S).

A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.

According to one embodiment, a substrate processing method is disclosed. The method can include treating a substrate with a first liquid. The substrate has a structural body formed on a major surface of the substrate. The method can include forming a support member supporting the structural body by bringing a second liquid into contact with the substrate wetted by the first liquid, and changing at least a portion of the second liquid into a solid by carrying out at least one of causing the second liquid to react, reducing a quantity of a solvent included in the second liquid, and causing at least a portion of a substance dissolved in the second liquid to be separated. The method can include removing the support member by changing at least a part of the support member from a solid phase to a gaseous phase, without passing through a liquid phase.

Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nanostructure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nanostructure may be formed as the thickest of the nanostructures in the vertical stack.

A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.