A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

A method for manufacturing an SOI wafer by performing a sacrificial oxidation treatment and reducing a thickness of an SOI layer of the SOI wafer, in which: the SOI wafer on which the sacrificial oxidation treatment is performed has a film thickness distribution with a one-way sloping shape; a thermal oxidation in the sacrificial oxidation treatment is performed by combining a non-rotating oxidation and a rotating oxidation, using a vertical heat treatment furnace; whereby a thermal oxide film having an oxide film thickness distribution with a one-way sloping shape canceling the film thickness distribution with a one-way sloping shape of the SOI layer, is formed on a surface of the SOI layer; and by removing the formed thermal oxide film, an SOI wafer having an SOI layer whose film thickness distribution with a one-way sloping shape has been resolved is manufactured.

The invention provides a method for manufacturing a SONOS memory, including: providing a substrate, wherein a selective transistor gate and a storage transistor gate are formed on the substrate of a storage area; forming a silicon epitaxial layer on the upper surface of the substrate of the storage area on both sides of the selective transistor gate and on both sides of the storage transistor gate, wherein the silicon epitaxial layer is used to separately form a source and a drain of a selective transistor and a storage transistor; and forming a metal salicide layer on an upper portion of the silicon epitaxial layer. The present application further provides the SONOS memory. The present application can improve the yield of the formed SONOS memory and effectively improve the device performance of the formed SONOS memory, and the device performance of the formed SONOS memory can be effectively improved.

The present application provides a method for manufacturing FDSOI devices. The method includes steps of: providing a semiconductor structure which comprises a silicon substrate, a buried oxide layer on the silicon substrate, a silicon-on-insulator layer on the buried oxide layer; and a hard mask layer on the silicon-on-insulator layer; performing spin coating of a photoresist on the hard mask layer to form a bulk silicon region; performing plasma anisotropic etching on the bulk silicon region to open a part of the buried oxide layer, and then performing isotropic etching, so that the silicon-on-insulator layer shrinks in the horizontal direction; performing plasma anisotropic etching to etch through the buried oxide layer to form a bulk silicon region trench; performing silicon epitaxial growth in the bulk silicon region trench. The silicon-on-insulator layer is still shrinks after the bulk silicon region trench is formed, as the result, there is no bump on the surface of the silicon-on-insulator layer, thus the process window becomes controllable.

A semiconductor device includes a semiconductor-on-insulator water having a buried layer. The buried layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.

A method of manufacturing a silicon on insulator substrate includes: preparing a semiconductor substrate including a rear side semiconductor layer, an insulating layer, and a front side semiconductor layer, a first surface of the insulating layer being in contact with a surface of the rear side semiconductor layer, and a first surface of the front side semiconductor layer being in contact with a second surface of the insulating layer; forming a high concentration region in which an impurity concentration is increased in the front side semiconductor layer, by injecting impurities into the front side semiconductor layer; heating the semiconductor substrate having the high concentration region; and epitaxially growing an additional semiconductor layer on a second surface of the front side semiconductor layer of the heated semiconductor substrate, the additional semiconductor layer having a lower impurity concentration than the high concentration region.

A semiconductor device includes a supporting substrate, an insulating film formed in a first region over the supporting substrate, a first semiconductor layer formed over the insulating film, a first epitaxial layer formed in an opening of the insulating film in a second region over the supporting substrate, an element isolation region formed between the first semiconductor layer and the first epitaxial layer, and a semiconductor element formed over each of the first semiconductor layer in the first region and the first epitaxial layer in the second region. The first semiconductor layer and the first epitaxial layer is spaced apart from each other by 5 μm or more.

A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.