Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

Provided are a method for transferring a compound semiconductor single crystal thin film layer and a method for preparing a single crystal GaAs—OI composite wafer, including: preparing a graphite transition layer on a first substrate; growing the compound semiconductor single crystal thin film layer on the graphite transition layer; preparing a first dielectric layer on the compound semiconductor single crystal thin film layer; preparing a second dielectric layer on a second substrate; combining the first substrate and the second substrate by bonding the first dielectric layer and the second dielectric layer; applying a lateral external pressure, such that the compound semiconductor single crystal thin film layer and the first substrate are transversely split at the graphite transition layer, and the compound semiconductor single crystal thin film layer is transferred to the second substrate.

An RF MOSFET includes respective pluralities of gate fingers, source fingers, and drain fingers formed on a semiconductor structure. The gate fingers are spaced apart from each other along a first direction, extend in a second, orthogonal direction, and are electrically connected to one another through a gate mandrel. The source fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a source mandrel. The drain fingers are spaced apart from each other along the first direction, extend in the second direction, and are electrically connected to one another through a drain mandrel. Adjacent unit cell transistors of the RF MOSFET are separated from one another by a dummy gate and a trench that extends into the semiconductor structure. The semiconductor structure may be a bulk semiconductor wafer, a PD-SOI wafer, or an FD-SOI wafer.

A production method for a semi-conductor-on-insulator type multilayer stack includes ion implantation in a buried portion of a superficial layer of a support substrate, so as to form a layer enriched with at least one gas, intended to form a porous semi-conductive material layer, the thermal oxidation of a superficial portion of the superficial layer to form an oxide layer extending from the surface of the support substrate, the oxidation and the implantation of ions being arranged such that the oxide layer and the enriched layer are juxtaposed, and the assembly of the support substrate and of a donor substrate.

A glass substrate has a compaction of 0.1 to 100 ppm. An absolute value |Δα.sub.50/100| of a difference between an average coefficient of thermal expansion α.sub.50/100 of the glass substrate and an average coefficient of thermal expansion of single-crystal silicon at 50° C. to 100° C., an absolute value |Δα.sub.100/200| of a difference between an average coefficient of thermal expansion α.sub.100/200 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 100° C. to 200° C., and an absolute value |Δα.sub.200/300| of a difference between an average coefficient of thermal expansion α.sub.200/300 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 200° C. to 300° C. are 0.16 ppm/° C. or less.

According to the present invention there is provided a method of depositing a hydrogenated silicon carbon nitride (SiCN:H) film onto a substrate by plasma enhanced chemical vapour deposition (PECVD) comprising the steps of: providing the substrate in a chamber; introducing silane (SiH.sub.4), a hydrocarbon gas or vapour, nitrogen gas (N.sub.2), and hydrogen gas (H.sub.2) into the chamber; and sustaining a plasma in the chamber so as to deposit SiCN:H onto the substrate by PECVD at a process temperature of less than about 200° C.

A front-side type image sensor may include a substrate successively including: a P− type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.