A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

The present disclosure relates to a semiconductor device and a preparation method thereof. The method for preparing a semiconductor device comprises: providing a first dielectric layer; forming a first window in the first dielectric layer; forming a first connection structure in the first window; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second window from which at least the first connection structure is exposed; forming a first barrier layer on the sidewall and bottom of the second window, the first barrier layer comprising an opening from which part of the first connection structure is exposed; and forming a second connection structure in the second window.

A method includes loading a wafer into a processing chamber, wherein the processing chamber is wound by a coil, and the coil is coupled to an RF system; supplying an aromatic hydrocarbon precursor into the processing chamber; after supplying the aromatic hydrocarbon precursor, turning on an RF power of the RF system to decompose the aromatic hydrocarbon precursor into active radicals and cyclize the active radicals into a graphene layer over a metal layer on the wafer; and after an entirety of the metal layer being covered by the graphene layer, turning off the RF power of the RF system to stop forming the graphene layer.

According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.

A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.

A plating apparatus and plating methods for plating metal layers on a substrate. In an embodiment, a plating method comprises: step 1: immersing a substrate into plating solution of a plating chamber assembly including at least a first anode and a second anode (3001); step 2: turning on a first plating power supply applied on the first anode, setting the first plating power supply to output a power value P.sub.11 and continue with a period T.sub.11 (3002); step 3: when the period T.sub.11 ends, adjusting the first plating power supply applied on the first anode to output a power value P.sub.12 and continue with a period T.sub.12, at the same time, turning on a second plating power supply applied on the second anode, and setting the second plating power supply to output a power value P.sub.21 and continue with a period T.sub.21 (3003); and step 4: when the period T.sub.21 ends, adjusting the second plating power supply applied on the second anode to output a power value P.sub.22 and continue with a period T.sub.22; wherein step 2 to step 4 are performed periodically.

A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.

A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ru

A method of manufacturing a semiconductor structure includes: forming a first opening in a first dielectric material; forming a first barrier layer in the first opening; forming a first seed material including copper and manganese on the first barrier layer, in which the manganese in the first seed material is in a range of from 0.10 at % to 0.40 at %; forming a first conductive material on the first seed material; and moving at least some of the manganese of the first seed material to a location proximate an interface between the first seed material and the first barrier layer. Another method of manufacturing a semiconductor structure and a semiconductor structure are also provided.