Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

A novel image processing method is provided. In a display device in which a video signal is individually supplied to a screen divided into two, the entire screen is subjected to up-conversion processing after being divided, and another up-conversion processing is performed for a boundary portion of the screen divided into two. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion are performed in parallel with the use of a plurality of arithmetic units. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion can be performed using different algorithms.

A 3D device, the device including: at least a first level including logic circuits; at least a second level including an array of memory cells; at least a third level including special circuits; and at least a fourth level including special connectivity structures, where the special connectivity structures include one of the following: a. waveguides, or b. differential signaling, or c. radio frequency transmission lines, or d. Surface Waves Interconnect (SWI) lines, and where the third level includes Radio Frequency (“RF”) circuits to drive the special connectivity structures, where the second level overlays the first level, where the third level overlays the second level, and where the fourth level overlays the third level.

A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

An embodiment of the invention may include a method of forming and a resulting multiply-and-accumulate device. The device may include a capacitor in a second region. The capacitor comprises a dielectric located between a first metal contact and a second metal contact. The device may include a stacked nanosheet device in the first region from the nanosheet. The stacked nanosheet device may include a top transistor and a bottom transistor in contact with the first metal contact. The device may include a nanosheet device in the third region, wherein a source/drain of a transistor of the nanosheet device is in contact with the first metal contact.

A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

A method of microfabrication includes forming an initial vertical channel structure of semiconductor material protruding from a surface of a substrate such that the initial vertical channel structure has a current flow path that is perpendicular to the surface of the substrate. The initial vertical channel structure is segmented lengthwise into a plurality of independent vertical channel structure segments, each vertical channel structure segment having a respective current flow path that is perpendicular to the surface of the substrate.

A semiconductor device include: a substrate; a 1.sup.st transistor formed above the substrate, the 1.sup.st transistor including a 1.sup.st channel set of a plurality of 1.sup.st nanosheet layers, a 1.sup.st gate structure surrounding the 1.sup.st nanosheet layers, and 1.sup.st and 2.sup.nd source/drain regions at both ends of the 1.sup.st channel set; and a 2.sup.nd transistor formed above the 1.sup.st transistor in a vertical direction, the 2.sup.nd transistor including a 2.sup.nd channel set of a plurality of 2.sup.nd nanosheet layers, a 2.sup.nd gate structure surrounding the 2.sup.nd nanosheet layers, and 3.sup.rd and 4.sup.th source/drain regions at both ends of the 2.sup.nd channel set, wherein the 1.sup.st channel set has a greater width than the 2.sup.nd channel set, wherein a number of the 1.sup.st nanosheet layers is smaller than a number of the 2.sup.nd nanosheet layers, and wherein a sum of effective channel widths of the 1.sup.st nanosheet layers is substantially equal to a sum of effective channel width of the 2.sup.nd nanosheet layers.

The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.