A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

An electrochemical sensor array includes a thermal oxide configured to interface with one or more analytes. There is a transistor device layer that includes a plurality of field effect transistors (FETs) on top of the thermal oxide. A contact and wiring structure layer is on top of the transistor device layer and operative to couple to control nodes of each of the plurality of FETs. The contact and wiring structure are on a side opposite to that of the thermal oxide.

An electrochemical sensor array includes a thermal oxide configured to interface with one or more analytes. There is a transistor device layer that includes a plurality of field effect transistors (FETs) on top of the thermal oxide. A contact and wiring structure layer is on top of the transistor device layer and operative to couple to control nodes of each of the plurality of FETs. The contact and wiring structure are on a side opposite to that of the thermal oxide.

The present invention relates to a high-frequency semiconductor device. A conventional high-frequency semiconductor device including an input second-order harmonic matching circuit has such a problem that gain decrease occurs. In a high-frequency semiconductor device (100) of the present invention, two adjacent unit transistor cells (7) and (8) are connected to one input second-order harmonic matching circuit (19) provided on an upper surface of a semiconductor substrate (1). The input second-order harmonic matching circuit (19) includes a first capacitor (13), a first inductor (14), a second capacitor (15), and a second inductor (16). The first capacitor (13) and the first inductor (14) resonate at the frequency of a fundamental wave, and each of impedances as seen by input electrodes of the two unit transistor cells (7) and (8) is short-circuited at the frequency of a second-order harmonic.

The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.

The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.

The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.

The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.

In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed as an elongated element that is formed into a pattern of a spiral. An embodiment of the pattern of the resistor includes a plurality of revolutions from the starting point to an ending point. The resistor material has one of a separation distance between adjacent revolutions that increases with distance along a periphery of the resistor material or a width of the resistor material that increases with distance along the periphery of the resistor material.

In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed as an elongated element that is formed into a pattern of a spiral. An embodiment of the pattern of the resistor includes a plurality of revolutions from the starting point to an ending point. The resistor material has one of a separation distance between adjacent revolutions that increases with distance along a periphery of the resistor material or a width of the resistor material that increases with distance along the periphery of the resistor material.