A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.

A semiconductor device including: a substrate in which a first transistor region and a second transistor region are provided; a first channel layer in which a carrier of a first conductivity type travels, the first channel layer being provided over the substrate in the first transistor region and including a compound semiconductor; a first impurity epitaxial layer of a second conductivity type that is provided over the substrate with the first channel layer interposed therebetween, is disposed in a first gate region in a central portion and outside the first gate region, and has a low concentration region in which an electric charge amount per unit length is small as compared to the first gate region; and a second channel layer in which a carrier of the second conductivity type travels, the second channel layer being provided over the substrate in the second transistor region and including a compound semiconductor.

A semiconductor device including: a substrate in which a first transistor region and a second transistor region are provided; a first channel layer in which a carrier of a first conductivity type travels, the first channel layer being provided over the substrate in the first transistor region and including a compound semiconductor; a first impurity epitaxial layer of a second conductivity type that is provided over the substrate with the first channel layer interposed therebetween, is disposed in a first gate region in a central portion and outside the first gate region, and has a low concentration region in which an electric charge amount per unit length is small as compared to the first gate region; and a second channel layer in which a carrier of the second conductivity type travels, the second channel layer being provided over the substrate in the second transistor region and including a compound semiconductor.

A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, a first transistor on the epitaxial layer, an interlayer dielectric layer on the epitaxial layer, a dielectric pillar penetrating through the interlayer dielectric layer and the epitaxial layer, and a conductive liner disposed on a sidewall of the dielectric pillar. The conductive liner is electrically connected to the first transistor and the seed layer.

A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, a first transistor on the epitaxial layer, an interlayer dielectric layer on the epitaxial layer, a dielectric pillar penetrating through the interlayer dielectric layer and the epitaxial layer, and a conductive liner disposed on a sidewall of the dielectric pillar. The conductive liner is electrically connected to the first transistor and the seed layer.

A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

A novel image processing method is provided.

In a display device in which a video signal is individually supplied to a screen divided into two, the entire screen is subjected to up-conversion processing after being divided, and another up-conversion processing is performed for a boundary portion of the screen divided into two. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion are performed in parallel with the use of a plurality of arithmetic units. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion can be performed using different algorithms.

A novel image processing method is provided.

In a display device in which a video signal is individually supplied to a screen divided into two, the entire screen is subjected to up-conversion processing after being divided, and another up-conversion processing is performed for a boundary portion of the screen divided into two. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion are performed in parallel with the use of a plurality of arithmetic units. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion can be performed using different algorithms.

Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.

Manufacturing processes leverage process steps used during CMOS formation to form one or more additional type(s) of devices on the same substrate used for the CMOS formation, and at least partially in parallel with the CMOS formation processes. A first layer of implant wells may be formed at a first depth in a substrate using a first mask, and then a second layer of implant wells may be formed at a second, more shallow depth, using a second mask. CMOS devices that are part of a CMOS platform may be formed using some of the wells, while peripheral devices may be formed using remaining wells.