The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type heavily doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type heavily doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

An Electrostatic Discharge protection circuit with low parasitic capacitance is provided, comprising a first bipolar junction transistor and a first ESD power clamp device. The first bipolar junction transistor is an NPN type of bipolar junction transistor, including a base and an emitter commonly connected to an I/O terminal and a collector connected with the first ESD power clamp device. The first ESD power clamp device is further connected to ground, and can be a Zener diode, PNP type, NPN type of bipolar junction transistor or the like. When a positive ESD pulse is injected, an ESD protection path is consisting of the first bipolar junction transistor and the first ESD power clamp device. When a negative ESD pulse is injected, the ESD protection path is consisting of a parasitic silicon controlled rectifier, thereby reducing parasitic capacitance effectively.

An integrated circuit includes a bipolar transistor, e.g. a back-ballasted NPN, that can conduct laterally and vertically. At a low voltage breakdown and low current conduction occur laterally near a substrate surface, while at a higher voltage vertical conduction occurs in a more highly-doped channel below the surface. A relatively high-resistance region at the surface has a low doping level to guide the conduction deeper into the collector.

A silicon-controlled rectifier (SCR) includes a semiconductor body including a first main surface and an active device region. First through fourth surface contact areas at the first main surface are arranged directly one after another along a lateral direction. The semiconductor body is electrically contacted at each surface contact area. First and third SCR regions of a first conductivity type directly adjoin the first and third surface contact areas, respectively. Second and fourth SCR regions of a second conductivity type directly adjoin the second and fourth surface contact areas, respectively. The second SCR region at least partially overlaps a first well region of the first conductivity type at the first main surface. The first SCR region at most partially overlaps the first well region at the first main surface, and is electrically connected to the second SCR region. The third SCR region is electrically connected to the fourth SCR region.

Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

A bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes, a clamp circuit including an MOS transistor integrated with a silicon controlled rectifier (SCR) and a trigger circuit. In response to a voltage applied to one of the protected nodes exceeding a first voltage level, the trigger circuit drives the MOS transistor to cause a current flow at the SCR to trigger an SCR action and the SCR clamps the voltage at the respective protected node at a clamping voltage. In other embodiments, a bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes with a clamp device merged with a steering diode in each set. In some embodiments, the TVS protection circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range.

In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

A data cable and a charging device. The data cable includes a Type-A interface, a first interface, and a cable, where a VBUS pin, a D+ pin, a D− pin, and a GND pin in each of the Type-A interface and the first interface are connected in a one-to-one correspondence; and the data cable is provided with a circuit identification module, where the circuit identification module includes a pull-up resistor, a switch circuit, and a filter circuit, a first terminal of the switch circuit is connected to a CC pin of the first interface, a second terminal is connected to a first terminal of the pull-up resistor, a third terminal is connected to a CC pin of the Type-A interface, where under the control of the filter circuit, the first terminal of the switch circuit is connected to the second terminal or the third terminal.

An electrostatic discharge protection device is provided. In particular, the present disclosure relates to a semiconductor device that is particularly useful for ESD protection purposes. The semiconductor device further includes a second electronic component integrated on the semiconductor body and being spaced apart from the first electronic component, the second electronic component includes a first secondary region of the first charge type and a second secondary region of the second charge type arranged adjacent to the first secondary region, and the second secondary region is electrically connected to the second device terminal; and a first capacitive element, a first terminal thereof being electrically connected to the second primary region, and a second terminal thereof being electrically connected to the first secondary region.