A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.

Provided is a radiation-tolerant 3D unit MOSFET having at least one selected from a dummy drain (DD), an N-well layer (NW), a deep N-well layer (DNW), and a P+ layer to minimize an influence by a total ionization dose effect and an influence by a single event effect.

A field-effect transistor including a gate electrode provided on a first-conductivity-type region of a semiconductor substrate with an insulating film provided between the gate electrode and the first-conductivity-type region, a source region of a second conductivity type provided in the semiconductor substrate on one of sides across the gate electrode, a drain region of the second conductivity type provided in the semiconductor substrate on the other of the sides, the other side facing the one side across the gate electrode, a first region of the first conductivity type provided below the drain region and having a higher concentration than the first-conductivity-type region, a second region of the first conductivity type provided to reach a surface in the semiconductor substrate on the other side and having a higher concentration than the first-conductivity-type region, and an extraction electrode connected to the second region.

A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node. An emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor. A gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor. Other embodiments are also described.

A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

An electrostatic discharge (ESD) protection circuit is provided. The ESD circuit includes a first transistor, a second transistor, and a silicon-controlled rectifier (SCR) circuit. The first transistor includes a first current electrode coupled at a first node, and a second current electrode and a control electrode coupled at a first voltage supply node. The second transistor includes a first current electrode, a second current electrode, and a control electrode. The control electrode of the second transistor is coupled at a body electrode of the first transistor. The SCR circuit includes an anode electrode coupled at the first node, a cathode electrode coupled at the first voltage supply node, and a trigger input coupled at the first current electrode of the second transistor.

The present disclosure provides an acceleration sensor including a sensor device and a signal processing device sealed in a single package. The sensor device is configured to generate an acceleration signal, and the signal processing device is configured to process the acceleration signal. The signal processing device includes a signal input terminal, a first electrostatic protection element and a second electrostatic protection element. The signal input terminal is configured to receive an external input of the acceleration signal. The first electrostatic protection element is configured to be connected between the signal input terminal and a first node to which a first voltage is applied. The second electrostatic protection element is configured to be connected between the signal input terminal and a second node to which a second voltage is applied. The first electrostatic protection element and the second electrostatic protection element have the same structure and leakage current characteristic.

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes an NMOS transistor configured to shunt current in response to an ESD pulse and a bigFET connected in parallel with the NMOS transistor. The NMOS transistor includes a source terminal, a gate terminal, and a body. The gate terminal and the body of the NMOS transistor are connected to the source terminal via a resistor. Other embodiments are also described.