The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region and the second source/drain region are configured to receive a first power voltage and a second power voltage, and are formed on the base region. The first electrostatic discharge region includes a first doped region and a first well. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region and a second well. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region.

A semiconductor device includes a semiconductor layer, a first region of a first conductivity type formed in the semiconductor layer and connected to a ground potential, a second region of a second conductivity type formed in the semiconductor layer, an insulating film formed on the semiconductor layer and covering the first region and the second region, an internal circuit, signal terminal for driving the internal circuit or to be driven by the internal circuit, a first wiring connecting the internal circuit and the signal terminal, a resistance element formed on the insulating film and interposed halfway through the first wiring, the resistance element including a first resistor facing the second region across the insulating film, and a second wiring connected to the first wiring on a side closer to the signal terminal than the resistance element and connecting the first wiring and the second region.

A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode.

Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.

Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.

A Freewheeling Diode of any kind (Fast Recovery Diode, Schottky Barrier Diode or other variants) is integrated with a Forced Extraction Device and in this way two entirely different functions—the Free-Wheeling function and the Forced Extraction function are combined in one device, simplifying the circuit and reducing the number of components. The FWD part of the integrated device is standard in the industry, but the Forced Extraction Device is made using a lateral or vertical PMOS with a votage capability between a control input and the output terminals that is as high or higher than the rating voltage of the Main Switch that will be used together with the FWD.

A III-nitride semiconductor based heterojunction power device including: a first heterojunction transistor formed on a substrate, and a second heterojunction transistor formed on the substrate. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor. The enhancement mode transistor acts as a main power switch, and the depletion mode transistor acts as a start-up component.

A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

A semiconductor device and a corresponding circuit for shunting current in a circuit protection configuration is disclosed. An example device includes a first semiconductor region having an anode electrical contact, a second semiconductor region having a cathode electrical contact, a third semiconductor region extending between the first semiconductor region and the second semiconductor region, the second semiconductor region and the third semiconductor region forming a PN junction therebetween, and a gate coupled to the third semiconductor region. The gate is controllable between a first mode in which additional space charges are induced in the semiconductor region to deplete the semiconductor region, and a second mode in which additional space charges are not induced in the semiconductor region.

Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.