Integrated circuits with enhanced EOS/ESD robustness and methods of designing same. One such integrated circuit includes a plurality of input/output pads, a positive voltage rail, a ground voltage rail, a collection of internal circuits representing the operational core of the integrated circuit, a plurality of input/output buffering circuits connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and a plurality of EOS/ESD protection circuits interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices. At least one of the EOS/ESD protection circuits is a MOSFET. The MOSFET has a source region having an accompanying ohmic contact. The MOSFET further has a rectifying junction contact in place of a drain region and accompanying ohmic contact.

A transistor device includes a substrate a first transistor structure. The first transistor structure includes a first fin structure on the substrate. The first fin structure includes a first doped region, and a second fin structure on the substrate spaced apart from the first fin structure. The second fin structure includes a second doped region and a third doped region spaced apart from the second doped region. The transistor device includes a first electrode on the second fin structure and covering a first end of the second fin structure.

The application relates to a device and method for measuring a high electron mobility transistor. The device provided includes a controller, a protection circuit, a load circuit and a switching circuit electrically connected between the load circuit and the protection circuit. The controller is configured to provide a first control signal having a first value to a semiconductor component at a first time point and provide a second control signal having a second value to the switching circuit at a second time point. The semiconductor component is turned on by the first value of the first control signal, and the switching circuit is turned on by the second value of the second control signal. The second time point is later than the first time point.

Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.

Integrated circuits with enhanced EOS/ESD robustness and methods of designing same. One such integrated circuit includes a plurality of input/output pads, a positive voltage rail, a ground voltage rail, a collection of internal circuits representing the operational core of the integrated circuit, a plurality of input/output buffering circuits connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and a plurality of EOS/ESD protection circuits interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices. At least one of the EOS/ESD protection circuits is a MOSFET. The MOSFET has a source region having an accompanying ohmic contact. The MOSFET further has a rectifying junction contact in place of a drain region and accompanying ohmic contact.

A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and the pad voltage terminal. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The fourth transistor is in a second well different from the first well, and is separated from the first well in a first direction.

A first gate drive outputs a first drive voltage to turn a first transistor on upon occurrence of a condition in which a voltage at a supply terminal is higher than a voltage at a ground terminal, the output first drive voltage being higher than the voltage at the ground terminal. A second gate drive outputs a second drive voltage to turn a second transistor on, upon occurrence of a condition in which the voltage at the supply terminal is lower than the voltage at the ground terminal, the output second drive voltage being higher than the voltage at the supply terminal.

An integrated circuit for power clamping is provided. The integrated circuit for power clamping is electrically coupled to an internal circuit of an integrated circuit through a power line and a ground line, and includes a switch, a first resistor, a capacitor, an inverter and a voltage detection circuit. The voltage detection circuit detects a voltage of the power line, and when the voltage of the power line exceeds a threshold value, the voltage detection circuit electrically connects a first node to the ground line, such that a low potential signal from the ground line is input to the input terminal of the inverter, and then the switch is turned on to form a discharge path.

A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.