An electrostatic discharge clamp is shown, which includes a clamping circuit, a driving circuit, a capacitor and resistor network, and a bias circuit. The clamping circuit has a plurality of transistors connected in a cascode configuration. The driving circuit is coupled to the gates of the transistors of the clamping circuit. The capacitor and resistor network introduces an RC delay in response to an electrostatic discharge event to control the driving circuit to turn on the transistors of the clamping circuit for electrostatic discharging. The bias circuit biases the driving circuit to turn off the transistors of the clamping circuit when the capacitor and resistor network does not detect the electrostatic discharge event.

An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method. The power clamp circuit is applied to a circuit system to monitor the power supply voltage of the circuit system and includes: an EOS protection module, for outputting an EOS protection triggering signal when it is determined that the circuit system is electrically overstressed based on the power supply voltage; an ESD protection module, for outputting an ESD protection triggering signal when it is determined that an electrostatic event is present in the circuit system based on the power supply voltage; a switch control module, for turning on a discharge path based on the EOS protection signal to discharge an EOS current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current.

A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.

In general, according to one embodiment, a protection circuit includes first and second power lines, first and second controllers, a first transistor, and a detector. The first controller includes a first resistor element, a capacitor, first, second, and third inverters. The second controller includes third transistor. One end of the third transistor is coupled to the second power line. The other end of the third transistor is coupled to each of the output end of the first inverter and the input end of the second inverter.

The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region and the second source/drain region are configured to receive a first power voltage and a second power voltage, and are formed on the base region. The first electrostatic discharge region includes a first doped region and a first well. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region and a second well. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region.

According to one embodiment, a semiconductor protection circuit includes a first MOS transistor that has a drain that is connected to an input terminal, a source that is connected to an output terminal, and a gate that is connected to a control terminal, a second MOS transistor that has a drain that is connected to the gate of the first MOS transistor and a source that is connected to the source of the first MOS transistor, a rectifier element that is connected in a forward direction from a gate of the second MOS transistor to the gate of the first MOS transistor, and a low-pass filter that is connected between the gate and the source of the second MOS transistor.

A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode.

An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.

An ESD protection circuit includes a trigger transistor that is responsive to a detection signal indicating an ESD event. The trigger transistor pulls the voltage of a hold node towards a voltage of a power supply rail in response to the detection signal indicating an ESD event. The ESD protection circuit includes a replica trigger transistor whose leakage current controls current provided to the hold node after the detection signal no longer indicates an ESD event to compensate for leakage current through the trigger transistor.