An electrostatic discharge (ESD) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region formed therein, and a plurality of insulating elements respectively formed therein. The plurality of insulating elements is respectively formed in a portion of the semiconductor layer between the first, second and third doped regions. The intrinsic region is formed at least in the semiconductor layer between one of the second and third regions and the other one of the second and third regions or between one of the second and third regions and the first region. The first doped region is formed with a first conductivity type, and the second and third doped regions are formed with a second conductivity type opposite to the first conductivity type.

A negative capacitance field effect transistor (NCFET) device is provided. The NCFET device includes a substrate, and a transistor stack structure formed on the substrate. The nanosheet stack structure includes a PFET region and an NFET region, the PFET region including a pWF metal layer stack and the NFET region including a nWF metal layer stack. The NCFET device also includes a dielectric interfacial layer formed on the transistor stack structure, the dielectric interfacial layer including metal induced oxygen vacancies, and the dielectric interfacial layer formed on a portion of the transistor stack structure. The NCFET device also includes a top electrode formed on the dielectric interfacial layer.

According to one embodiment, a semiconductor device includes a semiconductor member, a gate electrode, a source electrode, a drain electrode, a conductive member, a gate terminal, and a first circuit. The semiconductor member includes a first semiconductor layer including a first partial region and including Al.sub.x1Ga.sub.1−x1N (0≤x1≤1), and a second semiconductor layer including Al.sub.x2Ga.sub.1−x2N (0<x2≤1 and x1<x2). The first partial region is between the gate electrode and at least a portion of the conductive member in a first direction. The gate terminal is electrically connected to the gate electrode. The first circuit is configured to apply a first voltage to the conductive member based on a gate voltage applied to the gate terminal. The first voltage has a reverse polarity of a polarity of the gate voltage.

An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

A microelectronic device includes a substrate, at least two doped well regions, an epitaxial structure, and at least two power elements. The doped well regions are disposed in the substrate, and are spaced apart from each other. Each of the doped well regions has a doping type opposite to that of the substrate. The epitaxial structure is disposed on the substrate, and is in contact with the doped well regions. The power elements are disposed on the epitaxial structure opposite to the substrate, and are cascade connected with each other. A low potential terminal of each of the power elements is electrically connected to a respective one of the doped well regions. A method for making the microelectronic device is also provided.

According to an embodiment, a semiconductor device includes a first electrically conductive portion, a first semiconductor chip of a reverse-conducting insulated gate bipolar transistor, a second electrically conductive portion, a third electrically conductive portion, a second semiconductor chip of an insulated gate bipolar transistor, and a fourth electrically conductive portion. The first semiconductor chip includes a first electrode and a second electrode. The first electrode is electrically connected to the first electrically conductive portion. The second electrically conductive portion is electrically connected to the second electrode. The third electrically conductive portion is electrically connected to the first electrically conductive portion. The second semiconductor chip includes a third electrode and a fourth electrode. The third electrode is electrically connected to the third electrically conductive portion. The fourth electrically conductive portion is electrically connected to the fourth electrode and the second electrically conductive portion.

A method for producing a semiconductor device, the method includes, forming, on a substrate made from a semiconductor substance, at least one bipolar junction (BJ) transistor including a first terminal connected to a first well, the first well formed in the substrate and includes a first dopant having a first dopant concentration. At least one non-BJ transistor is formed on the substrate, the non-BJ transistor includes a second terminal connected to a second well, and the second well formed in the substrate and includes a second dopant having a same polarity as the first dopant. The first dopant concentration of the BJ transistor is higher than the second dopant concentration of the non-BJ transistor.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.