A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

An electric assembly includes a reverse conducting switching device and a rectifying device. The reverse conducting switching device includes transistor cells for desaturation configured to be, under reverse bias, turned on in a desaturation mode and to be turned off in a saturation mode. The rectifying device is electrically connected anti-parallel to the switching device. In a range of a diode forward current from half of a maximum rating diode current of the switching device to the maximum rating diode current, a diode I/V characteristic of the rectifying device shows a voltage drop across the rectifying device higher than a saturation I/V characteristic of the switching device with the transistor cells for desaturation turned off and lower than a desaturation I/V characteristic of the switching device with the transistor cells for desaturation turned on.

Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and a gated diode coupled to the access device. The gated diode may include a gate stack structure that includes a direct tunneling material, a trapping material, and a blocking material.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A semiconductor device according to the present invention includes a semiconductor layer of SiC of a first conductivity type, a plurality of body regions of a second conductivity type formed in the surface portion of the semiconductor layer with each body region forming a unit cell, a source region of the first conductivity type formed in the inner portion of the body region, a gate electrode facing the body region across a gate insulating film, a drain region of the first conductivity type and a collector region of the second conductivity type formed in the rear surface portion of the semiconductor layer such that the drain region and the collector region adjoin each other, and a drift region between the body region and the drain region, wherein the collector region is formed such that the collector region covers a region including at least two unit cells in the x-axis direction along the surface of the semiconductor layer.

A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.

A semiconductor device according to the present invention includes a semiconductor layer of SiC of a first conductivity type, a plurality of body regions of a second conductivity type formed in the surface portion of the semiconductor layer with each body region forming a unit cell, a source region of the first conductivity type formed in the inner portion of the body region, a gate electrode facing the body region across a gate insulating film, a drain region of the first conductivity type and a collector region of the second conductivity type formed in the rear surface portion of the semiconductor layer such that the drain region and the collector region adjoin each other, and a drift region between the body region and the drain region, wherein the collector region is formed such that the collector region covers a region including at least two unit cells in the x-axis direction along the surface of the semiconductor layer.

An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the s5emiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.