A semiconductor device includes a first transistor that flows a current to a load, a current generation circuit that outputs a current corresponding to a power consumption of the first transistor, a temperature sensor, a resistor-capacitor network coupled between the current generation circuit and the temperature sensor and an overheat detection circuit coupled to a connection point of the current generation circuit and the resistor-capacitor network, wherein the resistor-capacitor network comprises a resistor and a capacitor corresponding to a thermal resistance and a thermal capacitance between the first transistor and the temperature sensor.

In some aspects, the techniques described herein relate to a circuit including: a metal-oxide semiconductor field-effect transistor (MOSFET) including a gate, a source, and a drain; and a snubber circuit coupled between the drain and the source, the snubber circuit including: a diode having a cathode and an anode, the cathode being coupled with the drain; a capacitor having a first terminal coupled with the anode, and a second terminal coupled with the source; and a resistor having a first terminal coupled with the anode and the first terminal of the capacitor, and a second terminal coupled with the source.

A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.

FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.

A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.

The semiconductor device includes: a semiconductor substrate; a first transistor disposed above the semiconductor substrate and including a first source electrode, a first gate region, and a first drain electrode; and a second transistor disposed above the semiconductor substrate and including a second source electrode, a second gate region, and a second drain electrode. The first source electrode, the second gate region, and the second source electrode are substantially at an identical potential. The first drain electrode and the second drain electrode are substantially at an identical potential.

An RC IGBT includes: an active region with separate IGBT and diode sections; a semiconductor body forming a part of the active region; a first load terminal and control terminal at a first side of the body and a second load terminal at a second side, the control terminal including a control terminal finger that laterally overlaps, in the active region, with the diode section. Control trenches extending into the semiconductor body along a vertical direction have a control trench electrode electrically connected to the control terminal for controlling a load current between the load terminals in the IGBT section. At least one control trench extends into both IGBT and diode sections. The electrical connection between the control trench electrode of that control trench and the control terminal is established at least based on an electrically conductive member arranged, in the diode section, in contact with the control terminal finger.

A semiconductor device with an active transistor cell comprising a p-doped first and second base layers, surrounding an n type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional fortifying p-doped layers embedding the opposite ends of the trench recesses. The additional fortifying layers do not affect the active cell design in terms of cell pitch i.e., the design rules for transistor cell spacing, or hole drainage between the transistor cells, but reduce the gate-collector parasitic capacitance of the semiconductor, hence leading to optimum low conduction and switching losses. To further reduce the gate-collector capacitance, the trench recesses embedding the first gate electrodes can be formed with thicker insulating layers in regions that do not abut the first base layers, so as not to negatively impact the value of the threshold voltage.

A semiconductor device is proposed. The semiconductor device includes a semiconductor substrate including a RC-IGBT with a diode area. The diode area includes a p-doped anode region and an n-doped emitter efficiency adjustment region. At least one of the p-doped anode region or the n-doped emitter efficiency adjustment region includes deep level dopants.

A semiconductor structure includes a first nitride semiconductor layer; a second nitride semiconductor layer and a first conductive structure. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first conductive structure is disposed on the second nitride semiconductor layer. The first conductive structure functions as one of a drain and a source of a transistor and one of an anode and a cathode of a diode.