In an embodiment, a method of forming a neural network circuit may include forming a dielectric layer overlying a semiconductor substrate that has active devices formed in the semiconductor substrate. An opening may be formed in the dielectric layer, and a series connected resistor and diode may be formed within the opening.

A variable capacitance element is provided that includes a plurality of resistance elements that form a path for applying a control voltage to the electrodes of a plurality of variable capacitance portions connected in series. These resistance elements include first distribution resistance elements, second distribution resistance elements, a first shared resistance element, and a second shared resistance element. Moreover, vertical sectional areas of the first shared resistance element and the second shared resistance element with respect to conducting directions thereof are larger than the vertical sectional areas of the first distribution resistance elements and the second distribution resistance elements with respect to conducting directions thereof.

Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance.

Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.

In an embodiment, a method of forming a neural network circuit may include forming a dielectric layer overlying a semiconductor substrate that has active devices formed in the semiconductor substrate. An opening may be formed in the dielectric layer, and a series connected resistor and diode may be formed within the opening.

There is provided a semiconductor device including: a first semiconductor element including a first gate electrode, a first source electrode, and a first drain electrode; a second semiconductor element including a second gate electrode, a second source electrode, and a second drain electrode; a gate lead, a source lead, a first drain lead, and a second drain lead; and a resin part, wherein the first gate electrode and the first source electrode, and the first drain electrode are provided on opposite sides to each other in a first direction, wherein the second gate electrode and the second source electrode, and the second drain electrode are provided on opposite sides to each other in the first direction, wherein the first gate electrode and the second gate electrode are opposed to the first source electrode and the second source electrode, respectively, in the first direction.

Capacitor structures including a first island of a first conductive region and a second island of the first conductive region having a first conductivity type, an island of a second conductive region having a second conductivity type different than the first conductivity type, a dielectric overlying the first island of the first conductive region, a conductor overlying the dielectric, and a terminal of a diode overlying the second island of the first conductive region and overlying the island of the second conductive region.

Capacitor structures including a first island of a first conductive region and a second island of the first conductive region having a first conductivity type, an island of a second conductive region having a second conductivity type different than the first conductivity type, a dielectric overlying the first island of the first conductive region, a conductor overlying the dielectric, and a terminal of a diode overlying the second island of the first conductive region and overlying the island of the second conductive region.

A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.