Capacitor structures, and apparatus containing similar capacitor structures, might include a first conductive region having a first portion and second and third portions extending from an upper surface of its first portion, a second conductive region having a first portion and a second portion extending from an upper surface of its first portion, a dielectric overlying the second portion of the first conductive region, a conductor overlying the dielectric, and a conductive element overlying the third portion of the first conductive region and overlying the second portion of the second conductive region, wherein the first conductive region has a first conductivity type and the second conductive region has a second conductivity type different than the first conductivity type.

A semiconductor device includes a semiconductor die. A transient voltage suppression (TVS) structure is formed in the semiconductor die. A capacitor is formed over the semiconductor die. In one embodiment, the capacitor is formed by depositing a first conductive layer over the semiconductor die, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the semiconductor die. In another embodiment, the capacitor is formed by forming a trench in the semiconductor die, depositing an insulating material in the trench, and depositing a conductive material in the trench.

Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

A capacitor structure comprises a first conductive region having a first conductivity type and a second conductive region having a second conductivity type different than the first conductivity type. The first conductive region comprises a first protrusion portion and a second protrusion portion. The second conductive region comprises a protrusion portion. The capacitor structure further comprises a first dielectric overlying the first protrusion portion of the first conductive region, and a first conductor overlying the first dielectric. Additionally, the capacitor structure comprises a terminal of a diode overlying the second protrusion portion of the first conductive region and the protrusion portion of the second conductive region. The terminal of the diode comprises a second conductor isolated from the first conductor.

A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.

An One-Time Programmable (OTP) memory is built in at least one of semiconductor fin structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one fin. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one fin can be built on a common well or on an isolated structure that has at least one MOS gate dividing fins into at least one first active region and a second active region.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.

An electronic device includes first and second diffused resistors in contact with each other to form a PN junction. The device is configured so that a potential difference between the first and second resistors is constant at any point of the PN junction. The PN junction is reverse-biased.