An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants is blocked from the logic MOS transistors.

In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.

A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.

A bipolar junction transistor (BJT) containing sensor that includes a vertically orientated stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region in contact with a first sidewall of a vertically orientated base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region in contact with a second sidewall of the base region. The second extrinsic base region including a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.

An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography. A gate region of the transistor is formed by two spaced apart first trenches in that are filled with a doped semiconductor material, wherein the two spaced apart first trenches bound the channel region and set the critical dimension.

A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.

A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

A bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region. A first extrinsic base region is in contact with a first sidewall of a vertically oriented base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region is in contact with a second sidewall of the base region. The second extrinsic base region includes a sensing element. A sample trench is present adjacent to the BJT having a trench sidewall provided by the sensing element.