GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.

An electronic module for a half-bridge circuit includes a base substrate with an insulating layer between a first metal layer and a second metal layer. A trench formed through the first metal layer electrically isolates first, second, and third portions of the first metal layer from one another. A high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode of the depletion-mode transistor is connected to the first portion, a source electrode of the enhancement-mode transistor is connected to the second portion, a drain electrode of the enhancement-mode transistor is connected to a source electrode of the depletion-mode transistor, a gate electrode of the depletion-mode transistor is connected to the electrically conductive substrate, and the electrically conductive substrate is connected to the second portion.

The power device is formed by a D-mode HEMT and by a MOSFET in cascade to each other and integrated in a chip having a base body and a heterostructure layer on the base body. The D-mode HEMT includes a channel area formed in the heterostructure layer; the MOSFET includes a first and a second conduction region formed in the base body, and an insulated-gate region formed in the heterostructure layer, laterally and electrically insulated from the D-mode HEMT. A first metal region extends through the heterostructure layer, laterally to the channel area and in electrical contact with the channel area and the first conduction region.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A transistor module including a first transistor and a second transistor for start up control is provided. Wherein the first end of the first transistor is coupled to the first end of the second transistor, the second end of the first transistor is coupled to the control end of the second transistor, and the second end of the second transistor provides a start up current for a control circuit.

A novel and useful quantum computing machine includes classic computing and quantum computing cores. A programmable pattern generator executes instructions that control the quantum core. A pulse generator generates the control signals input to the quantum core to perform quantum operations. A partial readout of the quantum state is re-injected into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the readout before being re-injected into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or retrieved from classic memory where sequences of commands are stored in memory. A cryostat unit functions to cool the quantum computing core to approximately 4 Kelvin.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.