A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

Novel and useful electronic and magnetic control of several quantum structures that provide various control functions. An electric field provides control and is created by a voltage applied to a control terminal. Alternatively, an inductor or resonator provides control. An electric field functions as the main control and an auxiliary magnetic field provides additional control on the control gate. The magnetic field is used to control different aspects of the quantum structure. The magnetic field impacts the spin of the electron by tending to align to the magnetic field. The Bloch sphere is a geometrical representation of the state of a two-level quantum system and defined by a vector in x, y, z spherical coordinates. The representation includes two angles θ and φ whereby an appropriate electrostatic gate control voltage signal is generated to control the angle θ of the quantum state and an appropriate control voltage to an interface device generates a corresponding electrostatic field in the quantum structure to control the angle φ.

Novel and useful electronic and magnetic control of several quantum structures that provide various control functions. An electric field provides control and is created by a voltage applied to a control terminal. Alternatively, an inductor or resonator provides control. An electric field functions as the main control and an auxiliary magnetic field provides additional control on the control gate. The magnetic field is used to control different aspects of the quantum structure. The magnetic field impacts the spin of the electron by tending to align to the magnetic field. The Bloch sphere is a geometrical representation of the state of a two-level quantum system and defined by a vector in x, y, z spherical coordinates. The representation includes two angles θ and φ whereby an appropriate electrostatic gate control voltage signal is generated to control the angle θ of the quantum state and an appropriate control voltage to an interface device generates a corresponding electrostatic field in the quantum structure to control the angle φ.

A semiconductor device includes: a first nitride semiconductor layer having a first surface and a second surface facing the first surface; a first source electrode provided below the first surface; a first drain electrode provided below the first surface; a first gate electrode provided below the first surface and the first gate electrode being provided between the first source electrode and the first drain electrode; a second nitride semiconductor layer provided on the second surface, the second nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface facing the third surface and the second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer; a first silicon substrate provided on the fourth surface and the first silicon substrate having a fifth surface in contact with the fourth surface and a sixth surface facing the fifth surface; a second silicon substrate provided on the sixth surface and the second silicon substrate having a seventh surface bonded with the sixth surface and an eighth surface facing the seventh surface; a first semiconductor layer of first conductivity type provided on the second silicon substrate or in the second silicon substrate; a second semiconductor layer of first conductivity type provided on the first semiconductor layer and the second semiconductor layer having a lower concentration of impurities of first conductivity type than the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a second gate electrode provided above the first semiconductor layer, the second gate electrode facing the first semiconductor region with a gate insulating film interposed between the second gate electrode and the first semiconductor region; and a second source electrode provided on the second semiconductor region and the second source electrode being electrically connected to the second semiconductor region.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. A pull-down network for the switching-off of the high threshold voltage GaN transistor may be formed by additional auxiliary low-voltage GaN transistors and resistive elements connected with the low-voltage auxiliary GaN transistor.

A semiconductor structure includes a substrate having a first region and a second region, an epitaxial layer above the substrate, a first device on the first region, a second device on the second region and an isolation structure on the substrate. The first device includes a first gate electrode, a first source electrode and a first drain electrode disposed at two opposite sides of the first gate electrode. A dielectric layer disposed on the epitaxial layer covers the first gate electrode. The second device includes a second gate electrode disposed on the dielectric layer, second source and drain electrodes disposed at two opposite sides of the second gate electrode. The second source electrode is electrically connected to the first drain electrode. Also, the portions of the epitaxial layer respectively disposed in the first and second regions are isolated from each other by the isolation structure.

A semiconductor structure includes a substrate having a first region and a second region, an epitaxial layer above the substrate, a first device on the first region, a second device on the second region and an isolation structure on the substrate. The first device includes a first gate electrode, a first source electrode and a first drain electrode disposed at two opposite sides of the first gate electrode. A dielectric layer disposed on the epitaxial layer covers the first gate electrode. The second device includes a second gate electrode disposed on the dielectric layer, second source and drain electrodes disposed at two opposite sides of the second gate electrode. The second source electrode is electrically connected to the first drain electrode. Also, the portions of the epitaxial layer respectively disposed in the first and second regions are isolated from each other by the isolation structure.

Enhancement/depletion device pairs and methods of producing the same are disclosed. A disclosed example multilayered die includes a depletion mode device that includes a first polarization layer and a voltage tuning layer, and an enhancement mode device adjacent the depletion mode device, where the enhancement mode device includes a second polarization layer, and where the second polarization layer includes an opening corresponding to a gate of the enhancement mode device.

A semiconductor apparatus includes first, second and third transistors integrated in a monocrystal chip. Both the first and second transistors are vertical devices, each having a source node, a gate node and a drain node. The source node of the first transistor electrically connects to a primary source pin, the source node of the second transistor to a sample pin, and the gate nodes of the first and the second transistors to a control-gate pin. The third transistor is a vertical JFET with a source node, a control node and a drain node. The source node of the third transistor electrically connects to a charge pin, and the control node of the third transistor to a charge-control pin. All of the drain nodes of the first, second and third transistors are electrically connected to a high-voltage pin.