A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to first metal layer with a less than 40 nm alignment error; and a via disposed through the second level, where each of the second transistors includes a metal gate, and where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A semiconductor device includes a substrate having a first active region disposed in a first region of a substrate and a second active region disposed in a second region of the substrate. A first gate stack is disposed over the first active region and a second gate stack is disposed over the second active region, the first and second gate stacks having elongated shapes oriented in a first direction. A first metal layer is disposed over the first gate stack and the second gate stack. The first metal layer includes first metal layer structures oriented in a second direction orthogonal to the first direction. A second metal layer disposed over the first metal layer. The second metal layer includes second metal layer structures oriented in the first direction. A third metal layer is disposed over the second metal layer. The third metal layer includes a third metal layer structures oriented in the second direction.

A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

An integrated circuit according to some example embodiments of inventive concepts includes a substrate including a well including dopants of a first conductivity type, a first device region on the well, the first device region extending in a first direction parallel to the substrate, and a first isolation element inside the well, the first isolation element extending in the first direction. The first isolation element includes a first power rail configured to receive a power source voltage, and a first doping region between the first power rail and the well, the first doping region configured to transfer the power source voltage from the first power rail to the well, and including dopants of the first conductivity type.

A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

The present technology relates to an imaging element and a semiconductor chip that enable the imaging element to be shorter. A first chip including a photodiode, and a second chip including a circuit configured to process a signal from the photodiode are laminated, and an impurity layer is provided on a second surface opposite to a first surface of the second chip on which the first chip is laminated. The impurity layer is formed to have an impurity concentration higher than an impurity concentration of a semiconductor substrate constituting the second chip. In the present technology, for example, an imaging element that is configured by laminating a plurality of chips and is shorter and smaller can be applied.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

A 3D integrated circuit, the circuit including: a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second level is bonded to the first level, where the bonded includes metal to metal bonding, where the bonded includes oxide to oxide bonding, and where at least one of the second transistors include a replacement gate.