A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode including a plurality of electrodes independent from each other; a second electrode disposed to be opposed to the first electrode; an n-type photoelectric conversion layer including a semiconductor nanoparticle, the n-type photoelectric conversion layer being provided between the first electrode and the second electrode; and a semiconductor layer including an oxide semiconductor material, the semiconductor layer being provided between the first electrode and the n-type photoelectric conversion layer.

The present technology relates to an image sensor, an imaging device, and a ranging device capable of performing imaging so that noise is reduced. A photoelectric conversion unit configured to perform photoelectric conversion; a charge accumulation unit configured to accumulate charges obtained by the photoelectric conversion unit; a transfer unit configured to transfer the charges from the photoelectric conversion unit to the charge accumulation unit; a reset unit configured to reset the charge accumulation unit; a reset voltage control unit configured to control a voltage to be applied to the reset unit; and an additional control unit configured to control addition of capacitance to the charge accumulation unit are included. The charge accumulation unit includes a plurality of regions. The present technology can be applied to, for example, an imaging device that captures an image and a ranging device that performs ranging.

Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

A photoelectric conversion device includes a substrate provided with pixels each including a photoelectric converter that accumulates charge generated by an incidence of light, a charge holding portion that holds charge transferred from the photoelectric converter, and an amplifier unit that includes an input node that receives charge transferred from the charge holding portion, a metal film disposed over a side of a first surface of the substrate so as to cover at least the charge holding portion, and a trench structure provided in the substrate on the side of the first surface of the substrate. The photoelectric conversion device is configured such that the light is incident from the side of the first surface of the substrate. The trench structure is disposed between the photoelectric converter and the charge holding portion of a first pixel.

The incidence of incident light transmitted through a photoelectric conversion unit onto a charge holding unit, a pixel in the adjacency, and the like can be blocked in a pixel. An image sensor includes a pixel, a wiring layer, and an incident light attenuation unit. The pixel includes a photoelectric conversion unit that is formed in a semiconductor substrate and performs photoelectric conversion based on incident light, and a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion. The wiring layer is arranged on a surface of the semiconductor substrate different from a surface onto which the incident light is incident, and transports either the image signal or a signal applied to the pixel circuit. The incident light attenuation unit attenuates the incident light transmitted through the photoelectric conversion unit.

A unit cell for use in an optical active pixel sensor (APS) includes a photodiode having a first terminal connected to a photodiode biasing PDB line, and a second terminal opposite from the first terminal; a reset switch transistor having a first terminal connected to the second terminal of the photodiode, and a second terminal connected to a reference voltage line, and a gate of the reset switch transistor is connected to a reset signal RST supply line; and an amplification transistor having a first terminal connected to an output readout line, and a second terminal connected to a driving voltage supply line, and a gate of the amplification transistor is connected to a node constituting the connection of the second terminal of the photodiode and the first terminal of the reset switch transistor. An optical APS device includes a sensor matrix formed of a plurality of unit cells according to any of the embodiments arranged in an array of rows and columns.

A polarization imager is provided that includes a plurality of CMOS photodetectors and a plurality of polarization filters. Each of the plurality of CMOS photodetectors has a photodiode that is configured to operate in forward bias mode. Further, each of the plurality of polarization filters is monolithically integrated with a corresponding one of the plurality of CMOS photodetectors. Each of the plurality of photodiodes exhibits a logarithmic response to a flux of incident photons. The polarization imager achieves a dynamic range of at least 100 decibels with a signal-to-noise ratio of at least 60 decibels.

A semiconductor device includes an image sensor structure and a periphery device structure. The image sensor structure includes a first semiconductor substrate, a first interconnect structure, a radiation device, a transfer gate transistor electrically coupled to the radiation device, a floating diffusion region electrically coupled to the transfer gate, and a first capacitor disposed in the first interconnect structure. The transfer gate transistor electrically interconnects and disconnects the radiation device and the floating diffusion region. The periphery device structure includes a second interconnect structure disposed on the first interconnect structure, a second semiconductor substrate disposed on the second interconnect structure, a plurality of logic devices disposed in the second semiconductor substrate, and a second capacitor disposed in the second interconnect structure. The first capacitor and the second capacitor are electrically coupled to the floating diffusion region.

A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion.

A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.