An electromagnetic wave detector includes: a substrate; an insulating layer provided on the substrate; a graphene layer provided on the insulating layer; a pair of electrodes provided on the insulating layer, with the graphene layer being interposed therebetween; and buffer layers interposed between the graphene layer and the electrodes to separate the graphene layer and the electrodes from each other. The electromagnetic wave detector array includes arrayed electromagnetic wave detectors that are the same as or different from each other.

Provided is a radiation imaging apparatus, including: a plurality of pixels configured to output image signals corresponding to radiation; an image signal line configured to output the image signals; and a detection signal line configured to output a detection signal for detection of irradiation of the radiation, in which at least one of the plurality of pixels includes: a conversion element configured to convert the radiation into charge; a first switch configured to output the image signal corresponding to the charge via the image signal line; a storage capacitor including a first electrode and a second electrode, in which the first electrode is electrically connected to the conversion element to store the charge; and a second switch configured to electrically connect the second electrode and the detection signal line.

A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.

A solid-state imaging device comprises a first pixel group includes a first photoelectric conversion unit that converts into electric charges reflection light pulses from an object irradiated with an irradiation light pulse, a first electric charge accumulation unit accumulating the electric charges in synchrony with turning on the irradiation light pulses, and a first reset unit resetting the electric charges; and a second pixel group includes a second photoelectric conversion unit that converts the reflection light into electric charges, a second electric charge accumulation unit that accumulates the electric charges synchronously with a switching the irradiation light pulses from on to off, and a second reset unit that releases a reset of the electric charges converted by the second photoelectric conversion unit.

A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

A photoelectric conversion device includes a waveguide member disposed above a photoelectric conversion unit, and an insulating member disposed above a substrate, and surrounding at least part of the waveguide member. The waveguide member has a first side face, a second side face, and a third side face, arranged in that order from the substrate. An angle of inclination of the first side face is smaller than an angle of inclination of the second side face. An angle of inclination of the third side face is smaller than the angle of inclination of the second side face. The angle of inclination of the second side face is smaller than 90 degrees.

An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.

There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion.

An electronic device includes a first transistor, a second transistor, and a sensing circuit coupled to at least one of the first transistor and the second transistor. The sensing circuit includes a diode, a third transistor, and a fourth transistor. The diode has a first terminal. The third transistor has a first terminal and a second terminal. The first terminal of the third transistor is coupled to the first terminal of the diode. The fourth transistor has a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a data driver.

Some embodiments relate to an imaging system including an active pixel and an analog-to-digital conversion (ADC) circuit including comparator. The comparator may be operatively coupled to the active pixel and configured to receive an output of the active pixel. The back-end ADC and memory circuit may be operatively coupled to the active pixel. The back-end ADC and memory circuit may include a write control circuit, an ADC memory operatively coupled to a read/write data bus and to the write control circuit, and a state latch operatively coupled to the write control circuit.