An imaging apparatus includes a semiconductor substrate and a stack of layers of one or more dielectric materials and one or more conducting materials formed on the semiconductor substrate so as to define an array of pixel circuits including respective pixel electrodes at an upper layer of the stack of layers of one or more dielectric materials and one or more conducting materials and logic circuitry in an area adjacent to the array of pixel circuits. A light-absorbing layer is formed on the upper layer of the stack of layers of one or more dielectric materials and one or more conducting materials so as to overlie the area containing the logic circuitry and configured to absorb at least 90% of light that is incident on the light-absorbing layer. A layer of a photosensitive medium overlies the pixel electrodes.

Device and method of forming a device are disclosed. The device includes a substrate with a transistor component disposed in a transistor region and a micro-electrical mechanical system (MEMS) component disposed on a membrane over a lower sensor cavity in a hybrid region. The MEMS component serves as thermoelectric-based infrared sensor, a thermopile line structure which includes an absorber layer disposed over a portion of oppositely doped first and second line segments. A back-end-of-line (BEOL) dielectric is disposed on the substrate having a plurality of inter layer dielectric (ILD) layers with metal and via levels. The ILD layers include metal lines and via contacts for interconnecting the components of the device. The metal lines in the metal levels are configured to define a BEOL or an upper sensor cavity over the lower sensor cavity, and metal lines of a first metal level of the BEOL dielectric are configured to define a geometry of the MEMS component.

The invention relates to a method for manufacturing a first support (100) for forming, in particular with a functionalised second support (200), an optoelectronic component (1), the first support (100) comprising a semiconductor layer (110) and an alignment mark (140) provided on said semiconductor layer (110). The manufacturing method includes in particular a step of forming an aperture (141) in a semiconductor layer (110) comprising cadmium, a step of diffusing cadmium in a second location (142) of the aperture (141) and a cadmium sensitive etching step for promoting etching of one from the second location (142) which is rich in cadmium and the rest of a surface (110B) of the semiconductor layer (110). The invention also relates to a first support (100).

Examples of a pixel cell are disclosed. In one example, a pixel cell may include a first semiconductor layer including a photodiode and one or more transistor devices configured to convert charges generated by the photodiode into an analog signal. The pixel cell may also include a second semiconductor layer including one or more transistor devices configured to convert the analog signal to one or more digital signals. The first semiconductor layer and the second semiconductor layer may form a stack structure. In another example, a pixel cell may include a photodiode and a capacitor. The pixel cell may be operated, in a first mode of measurement, to measure the charges stored at the capacitor when the capacitor is electrically coupled with the photodiode, and in a second mode of measurement, to measure the charges stored at the capacitor when the capacitor is electrically isolated from the photodiode.

An integrated circuit assembly including a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer. The assembly can include a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished. The assembly can further include a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.

Multicolor, stacked detector devices, focal plane arrays including multicolor, stacked detector devices, and methods of fabricating the same are disclosed. In one embodiment, a stacked multicolor detector device includes a first detector and a second detector. The first detector includes a first detector structure and a first ground plane adjacent the first detector structure. The second detector includes a second detector structure and a second ground plane adjacent the second detector structure. At least one of the first ground plane and the second ground plane is transmissive to radiation in a predetermined spectral band. The first detector and the second detector are in a stacked relationship.

Methods of fabricating multicolor, stacked detector devices and focal plane arrays are disclosed. In one embodiment, a method of fabricating a stacked multicolor device includes forming a first detector by depositing a first detector structure on a first detector substrate, and depositing a first ground plane on the first detector structure, wherein the first ground plane is transmissive to radiation in a predetermined spectral band. The method further includes bonding an optical carrier wafer to the first ground plane, removing the first detector substrate, and forming a second detector. The second detector is formed by depositing a second detector structure on a second detector substrate, and depositing a second ground plane on the second detector structure. The method further includes depositing a dielectric layer on one of the first detector structure and the second ground plane, bonding the first detector to the second detector, and removing the second detector substrate.

In one example, a method comprises: exposing a first photodiode to incident light to generate first charge; exposing a second photodiode to the incident light to generate second charge; converting, by a first charge sensing unit, the first charge to a first voltage; converting, by a second charge sensing unit, the second charge to a second voltage; controlling an ADC to detect, based on the first voltage, that a quantity of the first charge reaches a saturation threshold, and to measure a saturation time when the quantity of the first charge reaches the saturation threshold; stopping the exposure of the first photodiode and the second photodiode to the incident light based on detecting that the quantity of the first charge reaches the saturation threshold; and controlling the ADC to measure, based on the second voltage, a quantity of the second charge generated by the second photodiode before the exposure ends.

Provided are a light receiving element and an electronic apparatus that prevent generation of a false signal due to light emission caused by a circuit. The light receiving element includes a plurality of pixels. Each of the plurality of pixels includes: a photoelectric conversion layer that photoelectrically converts incident light; a signal reading circuit including an in-pixel transistor that is provided on a side opposite to a light incident side surface of the photoelectric conversion layer, amplifies signal charge generated by the photoelectric conversion layer, and reads the signal charge out of a pixel array; and a metal junction that bonds the photoelectric conversion layer and the signal reading circuit. The metal junction covers the in-pixel transistor when viewed from the light incident side surface of the photoelectric conversion layer.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of semiconductor devices; a third level overlaying the second level, where the third level includes a plurality of image sensors, where the first level includes a plurality of landing pads, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.