An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and a plurality of pixel control circuits, where each of the plurality of image sensors is directly connected to at least one of the plurality of pixel control circuits, and where the integrated device includes a plurality of memory circuits.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and a plurality of pixel control circuits, where each of the plurality of image sensors is directly connected to at least one of the plurality of pixel control circuits, and where the integrated device includes a plurality of memory circuits.

Embodiments disclosed herein relate to a ROIC with a plurality of unit cells coupled to a detector array having a plurality of detectors for collecting photoelectrons over a plurality of temporal instances. An individual unit cell is electrically coupled to an individual detector to have one-to-one correspondence and includes one or more storage elements coupled to one or more programmable logic control switches. The storage element(s) store signal charges representing the photoelectrons while the programmable logic control switch(es) direct the signal charges from the storage element(s) at an individual temporal instance. A configuration of signal charges in the plurality of unit cells is mathematically operated as a three-dimensional matrix having a plurality of elements, where the three dimensions correspond to the two spatial dimensions of an individual unit cell and the individual temporal instance, and an individual element has a value corresponding to the number of signal charges stored therein.

A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.

Embodiments disclosed herein relate to a ROIC with a plurality of unit cells coupled to a detector array having a plurality of detectors for collecting photoelectrons over a plurality of temporal instances. An individual unit cell is electrically coupled to an individual detector to have one-to-one correspondence and includes one or more storage elements coupled to one or more programmable logic control switches. The storage element(s) store signal charges representing the photoelectrons while the programmable logic control switch(es) direct the signal charges from the storage element(s) at an individual temporal instance. A configuration of signal charges in the plurality of unit cells is mathematically operated as a three-dimensional matrix having a plurality of elements, where the three dimensions correspond to the two spatial dimensions of an individual unit cell and the individual temporal instance, and an individual element has a value corresponding to the number of signal charges stored therein.

A binning system includes a red-green-blue-infrared (RGB-IR) image sensor including at least one pixel group composed of 2?2 sub-groups, each having 2?2 pixels including two green pixels, one infrared pixels and one red or blue pixel, the 2?2 sub-groups being arranged such that the pixel group is half green, one quarter infrared, one eighth red and one eighth blue; and a digital binning device that performs pixel binning on at least one addend pixel to result in a binned pixel. The binned pixel and the at least one addend pixel are located in a same pixel group.

A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.