A semiconductor device structure includes a first S/D feature over a first device region of a substrate, a plurality of first semiconductor layers over the first device region of the substrate, and each first semiconductor layer is in contact with the first source/drain feature, a first gate electrode layer surrounding a portion of each first semiconductor layer, and a first dielectric spacer contacting the first S/D feature, the first dielectric spacer disposed between and in contact with two first semiconductor layers of the plurality of the first semiconductor layers. The substrate comprises a first dopant region underneath the first S/D feature and a second dopant region underneath first gate electrode layer and radial outwardly of the first dopant region, the first dopant region comprising first dopants having a first conductivity type and a first dopant concentration and the second dopant region comprising the first dopants having a second dopant concentration less than the first dopant concentration.

First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.

Various embodiments may provide an integrated circuit layout cell. The integrated circuit layout cell may include a doped region of a first conductivity type, a doped region of a second conductivity type opposite of the first conductivity type, and a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type. The integrated circuit cell may include a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal. The first controlled terminal and the second controlled terminal of the first transistor may include terminal regions of the second conductivity type formed within the further doped region of the first conductivity type. The integrated circuit cell may also include a second transistor.

Provided are a semiconductor device in which the lifetime of holes is controlled and the switching loss is suppressed, and a method of manufacturing the same. Provided are a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface, a first buffer layer of the first conductive type provided between the drift layer and the second main surface in contact with the drift layer, having a resistivity lower than that of the drift layer, and having an impurity concentration higher than that of the drift layer, and a high resistivity layer provided between the first buffer layer and the second main surface and having a resistivity higher than that of the drift layer.

A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers. Trenches penetrate through the second semiconductor region and reach the first semiconductor region. Each of the trenches may include a gate electrode, and an insulating film insulating the gate electrode from the first semiconductor region and the second semiconductor region. An upper electrode is electrically connected to the second semiconductor region and the third semiconductor region. A fourth semiconductor region of the second conductivity type is arranged on an outer side of the trench of which the gate electrode is an outermost gate electrode in a plan view. An edge trench is arranged on an outer side of the fourth semiconductor region. The fourth semiconductor region is electrically connected to the upper electrode and a bottom of the fourth semiconductor may be arranged deeper than a bottom of the second semiconductor region.

Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.

A silicon carbide semiconductor device is a SiC-SBD that has, in an active region, at a front surface of a semiconductor substrate containing silicon carbide, a mixture of a SBD structure having Schottky barrier junctions between a titanium film that is a lowermost layer of a front electrode and an n.sup.−-type drift region, and a JBS structure having pn junction portions between p-type regions and the n.sup.−-type drift region. The p-type regions form ohmic junctions with the titanium film that is the lowermost layer of the front electrode. After an ion implantation for the p-type regions, activation annealing is performed at a temperature in a range of 1700 degrees C. to 1900 degrees C. for a treatment time exceeding 20 minutes, whereby contact resistance between the titanium film and the p-type regions is adjusted to be in a range of about 5×10.sup.−4 Ω.Math.cm.sup.2 to 8×10.sup.−3 Ω.Math.cm.sup.2.

A semiconductor device is provided, wherein a semiconductor substrate includes: a first trench portion provided from a front surface of the semiconductor substrate to a predetermined depth, and having a longer portion and a shorter portion as seen from above; and a first conductivity-type floating semiconductor region at least partially exposed on the front surface and surrounded by the first trench portion, an interlayer insulating film has openings to electrically connect an emitter electrode and the floating semiconductor region, the openings include: a first opening closest to an outer end of the floating semiconductor region in a direction parallel to the longer portion; and a second opening second closest to the outer end in the direction parallel to the longer portion, and a distance between the first opening and the second opening is shorter than a distance between any adjacent two of the openings other than the first opening.

Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.

A semiconductor device has a cell part and a terminal part set in the device. The terminal part encloses the cell part. The semiconductor device includes a first electrode, a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, and an insulating layer. The first semiconductor layer is formed above the first electrode. The second semiconductor layer is provided in an upper portion of the first semiconductor layer, and has an impurity concentration profile along a vertical direction including a plurality of peaks. The insulating layer is provided on the second semiconductor layer.