An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.

A manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region; forming first gate oxide layers in a non-gate region of the high-voltage device region and the low-voltage device region and a second gate oxide layer in a gate region of the high-voltage device region; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; forming a first polysilicon gate and a first sidewall structure on the surface of the first gate oxide layer of the low-voltage device region and a second polysilicon gate and a second sidewall structure on the surface of the second gate oxide layer; the width of the second gate oxide layer is greater than the width of the second polysilicon gate; performing source drain ions injection to form a source drain extraction region; after depositing a metal silicide area block (SAB), performing a photolithographic etching on the metal SAB and forming metal silicide. The above manufacturing method of a semiconductor device simplifies process steps and reduces process cost. The present invention also relates to a semiconductor device.

Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.