A method of forming a vertical channel transistor includes forming a first source-drain (SD) contact on a first surface of a semiconductor device layer; and forming a second SD contact layer on a second surface of the semiconductor device layer, the second surface being opposite to the first surface. The semiconductor device layer is pattern etched to form a vertical channel structure having a first end connected to the first SD contact and a second end opposite to the first end and connected to the second SD contact. A gate-all-around (GAA) structure is formed to completely surrounding at least a portion of the vertical channel structure at a position between the first SD contact and the second SD contact.

A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.

Provided are a nano-structure assembly including an insulating substrate; and a nano-structure formed on the insulating substrate, and a nano-device including the same.

A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.

A field effect transistor (FET) for an nFET and/or a pFET device including a fin having a stack of nanowire-like channel regions. The stack includes at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region. The FET includes source and drain electrodes on opposite sides of the fin. The FET also includes a dielectric separation region including SiGe between the first and second nanowire-like channel regions extending completely from a surface of the second channel region facing the first channel region to a surface of the first channel region facing the second channel region. The FET includes a gate stack extending along a pair of sidewalls of the stack. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions.

A method for manufacturing a semiconductor device includes forming a source and region in a substrate. A core channel region is formed adjacent the source region. A barrier layer is formed adjacent the core channel region. A drain region is formed in the substrate such that the barrier layer is between the core channel region and the drain region. A first portion of a shell is formed along the core channel region. A second portion of the shell is formed along the barrier layer. The second portion of the shell includes a different material than the first portion of the shell.

A nanorod semiconductor layer having a flat upper surface, a micro-LED including the nanorod semiconductor layer, a pixel plate including the micro-LED, a display device including the pixel plate, and an electronic device including the pixel plate are provided. The nanorod semiconductor layer includes: a main body; and an upper end formed from the main body, wherein the upper end includes: a first inclined surface; a second inclined surface facing the first inclined surface; and a flat upper surface between the first inclined surface and the second inclined surface, and a width of the upper end becomes narrower in an upward direction, and when a length of the upper end protruded from the main body (a thickness of the upper end) is L1, an inclination angle between a surface extending parallel to a surface selected from the first and second inclined surfaces and the flat upper surface is β, and a width of the main body is D, a width D1 of the flat upper surface satisfies Equation 1.
D1=D−(2×L1×tan β)  <Equation 1>

A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.

Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

A memory structure, device, and method of making the same, the memory structure including: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; a gate electrode surrounding the high-k dielectric layer; and a memory cell electrically connected to the drain electrode and a bit line. The memory cell includes a first electrode that is electrically connected to the drain electrode.