A semiconductor device includes a drift layer, a channel layer, a source layer being the first conductivity type, a gate layer, a body layer, a shield layer and a drain layer. The channel is disposed on the drift layer. The source layer is disposed on a surface layer portion of the channel layer. The gate layer is arranged to be deeper than the source layer. The body layer is arranged to be deeper than the source layer. The shield layer is disposed at a portion of the channel layer between the gate layer and the drift layer. The shield layer is maintained at a potential different from a potential of the gate layer. The drain layer is disposed at a side opposite to the channel layer. A depth ratio of a depth of the gate layer to a depth of the body layer is equal to or larger than 0.45.

A transistor arrangement and a method are disclosed. The transistor arrangement includes: a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, the first semiconductor regions and the second semiconductor regions being arranged alternatingly in a vertical direction of a semiconductor body; a source region adjoining the plurality of first semiconductor regions; a drain region adjoining the plurality of second semiconductor regions and arranged spaced apart from the source region in a first lateral direction; and a plurality of gate regions each of which adjoins at least one of the plurality of second semiconductor regions and is arranged between the source region and the drain region. At least one of the first and semiconductor regions, but less than each of the first and second semiconductor regions has a doping dose that varies in the first lateral direction.

A logic gate cell structure is disclosed. The logic gate cell structure includes a substrate, a channel layer disposed over the substrate, and a field-effect transistor (FET) contact layer disposed over the channel layer. The FET contact layer is divided by an isolation region into a single contact region and a combined contact region. The channel layer and the FET contact layer form part of a FET device. A collector layer is disposed within the combined contact region over the FET contact layer to provide a current path between the channel layer and the collector layer though the FET contact layer. The collector layer, a base layer, and an emitter layer form part of a bipolar junction transistor.

An embodiment relates to a semiconductor component, comprising a semiconductor body of a first conductivity type comprising a voltage blocking layer and islands of a second conductivity type on a contact surface and optionally a metal layer on the voltage blocking layer, and a first conductivity type layer comprising the first conductivity type not in contact with a gate dielectric layer or a source layer that is interspersed between the islands of the second conductivity type.

A method of forming an alignment contact includes: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.

A junction field effect transistor includes a first semiconductor layer of first conductivity type, an element isolation insulator disposed on the first semiconductor layer to partition an active area, a second semiconductor layer of second conductivity type, on the first semiconductor layer in the active area, and having an end in a first direction separated from the element isolation insulator, a source layer of second conductivity type, on the second semiconductor layer, the source layer having an impurity concentration higher than that of the second semiconductor layer, a drain layer of second conductivity type, on the second semiconductor layer, and separated from the source layer in a second direction, the drain layer having an impurity concentration higher than that of the second semiconductor layer, and a gate layer of first conductivity type, on the second semiconductor layer, and between and separated from the source and drain layers.

A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels. In some embodiments, the junction gates are formed all-around the channel surfaces. As a result, the current flowing in the channels between the source and drain can be controlled with less voltage applied to the gates and less power consumption.

A semiconductor device includes: a drift region of a first conductive type including a contact section and extension sections extending along the main surface of a substrate; column regions of a second conductive type which alternate with the extension sections in a perpendicular direction to the extension direction of the extension sections and each includes an end connecting to the contact section; a well region of a second conductive type which connects to the other end of each column region and tips of the extension sections; and electric field relaxing electrodes which are provided above at least some of residual pn junctions with an insulating film interposed therebetween. Herein, the residual pn junctions are pn junctions other than voltage holding pn junctions formed in interfaces between the extension sections and the column regions.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.