A bidirectional electrostatic discharge protection device and a method for fabricating the same is disclosed. The protection device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, a second semiconductor epitaxial layer, a heavily-doped area, and a lightly-doped area. The substrate, the heavily-doped area, and the lightly-doped area have a first conductivity type and the epitaxial layers have a second conductivity type. The first semiconductor epitaxial layer and the second semiconductor epitaxial layer are sequentially formed on the substrate, and the heavily-doped area and the lightly-doped area are formed in the second semiconductor epitaxial layer. The lightly-doped area covers the corner of the heavily-doped area, and the breakdown voltage of a junction between the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer corresponds to the breakdown voltage of a junction between the second semiconductor epitaxial layer and the heavily-doped area.

A transient voltage suppressor (TVS) device includes a MOS-triggered silicon controlled rectifier (SCR) as the high-side steering diode and a silicon controlled rectifier (SCR) for the low-side steering diode. In one embodiment, the MOS-triggered SCR includes alternating p-type and n-type regions and a diode-connected MOS transistor integrated therein to trigger the silicon controlled rectifier to turn on. In one embodiment, the SCR of the low-side steering diode includes alternating p-type and n-type regions where the p-type region adjacent the n-type region forming the cathode terminal is not biased to any electrical potential.

A semiconductor memory device according to an embodiment includes a substrate, a source line, a plurality of word lines, a pillar, and a first contact portion. The word lines are spaced apart from each other in a first direction. A bottom portion of the pillar reaches the source line. The first contact portion is provided on the substrate. The first contact portion is connected between the source line and the substrate. An inside of the first contact portion, or a portion in which a conductive layer included in the source line is in contact with the first contact portion, includes a portion functioning as a diode. The portion functioning as the diode is electrically connected in a reverse direction from the source line toward the substrate.

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type heavily doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type heavily doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A stack of alternating nanosheets of sacrificial semiconductor material nanosheets and semiconductor material nanosheets located on a surface of a substrate are provided, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack. End portions of each of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer is formed within each recess. Doped semiconductor portions are formed on the physically exposed sidewalls of each semiconductor material nanosheet and on the surface of the substrate. The semiconductor structure is thermally annealed. The sacrificial gate, each sacrificial semiconductor material nanosheet, and the dielectric spacer are each removed. A doped epitaxial material structure is formed in regions occupied by each sacrificial semiconductor material nanosheet, where the doped epitaxial material structure wraps around each suspended semiconductor material nanosheet.

A transient-voltage-suppression diode structure and a manufacturing method thereof are disclosed. The structure includes a P type base substrate, an N type epitaxial layer, a P+ type implant layer, an N+ type implant layer, a plurality of deep trench portions, an interlayer dielectric layer and a first metal layer. The N type epitaxial layer is disposed on the P type base substrate. The P+ type implant layer and the N+ type implant layer are embedded within the N type epitaxial layer. The deep trench portions pass through the N type epitaxial layer and are connected with the P type base substrate. The first metal layer is disposed on the interlayer dielectric layer and connected with the P+ type implant layer, the N+ type implant layer, and the deep trench portions. The deep trench portions connected with the first metal layer are configured to form a silicon controlled rectifier.

In one embodiment, an asymmetric TVS device may include a semiconductor substrate, comprising an inner region, the inner region having a first polarity, and a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity, opposite the first polarity. The asymmetric TVS device may also include a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface, wherein the first surface region comprises a first dopant concentration, and wherein the second surface region comprises a second dopant concentration, greater than the first dopant concentration.

A bidirectional Zener diode includes a substrate, a first conductivity type base region formed at a front surface portion of the substrate, a second conductivity type first impurity region formed at the base region, a second conductivity type second impurity region formed at the base region away from the first impurity region, an insulating layer formed on a front surface of the substrate, a first electrode film formed on the insulating layer and electrically connected to the first impurity region, and a second electrode film formed on the insulating layer and electrically connected to the second impurity region, and a first region formed on the insulating layer, the first region being sandwiched between the first electrode film and the second electrode film, and the first region including a portion having an aspect ratio of 1 or larger.

ESD protection devices and methods are provided. In at least one embodiment, a device includes a first stack that forms a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type located therein. The first area is flush with a surface of the substrate. A second stack forms a diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of the second conductivity type having a second region of the first conductivity type located therein. The second area is flush, opposite the first stack, with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, on and in contact with the second stack.

A transient voltage suppressor (TVS) device uses a punch-through silicon controlled rectifier (SCR) structure for the low-side steering diode where the punch-through SCR structure realizes low capacitance at the protected node. In some embodiments, the punch-through silicon controlled rectifier of the low-side steering diode includes a first doped region formed in a first epitaxial layer, a first well formed spaced apart from the first doped region where the first well is not biased to any electrical potential, and a second doped region formed in the first well. The first doped region, the first epitaxial layer, the first well and the second doped region form the punch-through silicon controlled rectifier, with the first doped region forming the anode and the second doped region forming the cathode of the punch-through silicon controlled rectifier.